Datasheet > OR4E061BA352-DB

OR4E061BA352-DB

更新时间： 2024-11-18 15:47:07

品牌	Logo	应用领域
莱迪思 - LATTICE		时钟栅可编程逻辑
页数	文件大小	规格书
151页	2561K
描述
Field Programmable Gate Array, 2024 CLBs, 515000 Gates, 66MHz, 16192-Cell, CMOS, PBGA352, PLASTIC, BGA-352

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

OR4E061BA352-DB 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	PLASTIC, BGA-352	针数：	352
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.91
其他特性：	MAXIMUM USABLE GATES 1095000	最大时钟频率：	66 MHz
CLB-Max的组合延迟：	1.1 ns	JESD-30 代码：	S-PBGA-B352
长度：	35 mm	可配置逻辑块数量：	2024
等效关口数量：	515000	输入次数：	262
逻辑单元数量：	16192	输出次数：	262
端子数量：	352	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2024 CLBS, 515000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA352,26X26,50	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	1.5,3.3 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	2.54 mm
子类别：	Field Programmable Gate Arrays	最大供电电压：	1.575 V
最小供电电压：	1.425 V	标称供电电压：	1.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	35 mm
Base Number Matches：	1

OR4E061BA352-DB 数据手册

Data Sheet

September, 2002

ORCA Series 4 FPGAs

■ Traditional I/O selections:

— LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V)

I/Os.

Introduction

Built on the Series 4 reconﬁgurable embedded sys-

tem-on-chip (SoC) architecture, Lattice introduces its

new family of generic ﬁeld-programmable gate arrays

(FPGA). The high-performance and highly versatile

architecture brings a new dimension to bringing net-

work system designs to market in less time than ever

before. This new device family offers many new fea-

tures and architectural enhancements not available

in any earlier FPGA generations. Bringing together

highly ﬂexible SRAM-based programmable logic,

powerful system features, a rich hierarchy of routing

and interconnect resources, and meeting multiple

interface standards, the Series 4 FPGA accommo-

dates the most complex and high-performance intel-

lectual property (IP) network designs.

— Per pin-selectable I/O clamping diodes provide

3.3 V PCI compliance.

— Individually programmable drive capability:

24 mA sink/12 mA source, 12 mA sink/6 mA

source, or 6 mA sink/3 mA source.

— Two slew rates supported (fast and slew-lim-

ited).

— Fast-capture input latch and input ﬂip-ﬂop

(FF)/latch for reduced input setup time and zero

hold time.

— Fast open-drain drive capability.

— Capability to register 3-state enable signal.

— Off-chip clock drive capability.

— Two-input function generator in output path.

■ New programmable high-speed I/O:

— Single-ended: GTL, GTL+, PECL, SSTL3/2

(class I and II), HSTL (Class I, III, and IV), ZBT,

and DDR.

— Double-ended: LDVS, bused-LVDS, and

LVPECL. Programmable (on/off) internal parallel

termination (100 Ω) also supported for these

I/Os.

Programmable Features

■ High-performance platform design:

— 0.16 µm 7-level metal technology.

— Internal performance of >250 MHz.

— I/O performance of >420 MHz.

— Meets multiple I/O interface standards.

— 1.5 V operation (30% less power than 1.8 V

operation) translates to greater performance.

Table 1. ORCA Series 4—Available FPGA Logic

EBR

Blocks

EBR Bits

(K)

Usable*

Gates (K)

Device

Rows

Columns

PFUs

User I/O

LUTs

OR4E02

OR4E04

OR4E06

624

1296

2024

405

466

4,992

10,368

16,192

260—515

380—800

515—1095

111

147

* The usable gate counts range from a logic-only gate count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The

logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and

12 gates per SLIC/FF pair (one per PFU). Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic,

CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512

gates) per PFU. Embedded block RAM (EBR) is counted as four gates per bit plus each block has an additional 25 K gates.

7 K gates are used for each PLL and 50K gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs

are conservatively utilized in the gate count calculations.

Note: Devices are not pinout compatible with ORCA Series 2/3.

12 3 4 5 6 7...151

中文翻译

下载PDF

与OR4E061BA352-DB相关器件

型号	品牌	获取价格	描述	数据表
OR4E06-1BA352I	LATTICE	获取价格	ORCASeries 4 FPGAs
OR4E06-1BA680I	LATTICE	获取价格	Field Programmable Gate Array
OR4E06-1BAN352C	LATTICE	获取价格	Field Programmable Gate Array, 2024 CLBs, 471000 Gates, 420MHz, CMOS, PBGA352, PLASTIC, BG
OR4E06-1BAN352I	LATTICE	获取价格	Field Programmable Gate Array, 2024 CLBs, 471000 Gates, 420MHz, CMOS, PBGA352, PLASTIC, BG
OR4E06-1BM680C	LATTICE	获取价格	ORCASeries 4 FPGAs
OR4E061BM680-DB	LATTICE	获取价格	Field Programmable Gate Array, 2024 CLBs, 515000 Gates, 66MHz, 16192-Cell, CMOS, PBGA680,
OR4E06-1BM680I	LATTICE	获取价格	ORCASeries 4 FPGAs
OR4E06-1BMN680C	LATTICE	获取价格	Field Programmable Gate Array, 2024 CLBs, 471000 Gates, 420MHz, CMOS, PBGA680, PLASTIC, FB
OR4E06-2BA352C	LATTICE	获取价格	ORCASeries 4 FPGAs
OR4E062BA352-DB	LATTICE	获取价格	Field Programmable Gate Array, 2024 CLBs, 515000 Gates, 66MHz, 16192-Cell, CMOS, PBGA352,

与OR4E061BA352-DB相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

18
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

43
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

38

产品中心

服务支持

精选活动

关于我们

帮助中心

OR4E061BA352-DB

OR4E061BA352-DB 技术参数

OR4E061BA352-DB 数据手册

与OR4E061BA352-DB相关器件

与OR4E061BA352-DB相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

OR4E061BA352-DB

OR4E061BA352-DB 技术参数

OR4E061BA352-DB 数据手册

与OR4E061BA352-DB相关器件

与OR4E061BA352-DB相关文章

您还可以找

您在本页遇到什么问题？