Datasheet > OR4E04-1BM416C

OR4E04-1BM416C

更新时间： 2024-01-08 10:18:19

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
152页	2702K
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ORCASeries 4 FPGAs

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OR4E04-1BM416C 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	PLASTIC, FBGA-416
针数：	416	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.92	其他特性：	MAXIMUM NO OF USABLE GATES IS 643000
最大时钟频率：	420 MHz	CLB-Max的组合延迟：	1.1 ns
JESD-30 代码：	S-PBGA-B416	长度：	27 mm
湿度敏感等级：	3	可配置逻辑块数量：	1296
等效关口数量：	333000	输入次数：	290
逻辑单元数量：	10368	输出次数：	290
端子数量：	416	最高工作温度：	70 °C
最低工作温度：		组织：	1296 CLBS, 333000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA416,26X26,40	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	1.5/3.3 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	2.38 mm
子类别：	Field Programmable Gate Arrays	最大供电电压：	1.575 V
最小供电电压：	1.425 V	标称供电电压：	1.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	27 mm

OR4E04-1BM416C 数据手册

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Product Description ^(continued)

EMBEDDED

BLOCK RAM

HIGH-SPEED I/Os

EMBEDDED

MICROPROCESSOR

INTERFACE (MPI)

REPLACED BY

EMBEDDED IP

CORE FOR FPSCs

SYSTEM BUS

CLOCK PINS

(ALL 4 SIDES)

PFU

SLIC

PLC

PIO

FPGA/SYSTEM

BUS INTERFACE

PLLs

(ALL 4

CORNERS)

Note: For FPSCs, all I/Os and the four PLLs on the right side of the device are replaced with the embedded core.

5-7536(F)a

Figure 1. Series 4 Top Level Diagram

Programmable Logic Cells

The PLCs are arranged in an array of rows and columns. The location of a PLC is indicated by its row and column

so that a PLC in the second row and the third column is R2C3. The array of actual PLCs for every device begins

with R3C2 in all Series 4 generic FPGAs. PIOs are located on all four sides of the FPGA. Every group of four PIOs

on the device edge have an associated PIC.

The PLC consists of a PFU, SLIC, and routing resources. Each PFU within a PLC contains eight

4-input (16-bit) LUTs, eight latches/FFs, and one additional FF that may be used independently or with arithmetic

functions.The PFU is the main logic element of the PLC, containing elements for both combinatorial and sequential

logic. Combinatorial logic is done in LUTs located in the PFU. The PFU can be used in different modes to meet dif-

ferent logic requirements. The LUTs twin-quad architecture provides a conﬁgurable medium-/large-grain architec-

ture that can be used to implement from one to eight independent combinatorial logic functions or a large number

of complex logic functions using multiple LUTs. The ﬂexibility of the LUT to handle wide input functions, as well as

multiple smaller input functions, maximizes the gate count per PFU while increasing system speed.

The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled independently.

Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects.

LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit

modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be con-

ﬁgured as a synchronous 32x4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT

outputs or directly from invertible PFU inputs, or they can be tied high or tied low.The FFs also have programmable

clock polarity, clock enables, and local set/reset.

Lattice Semiconductor

1...3 4 567 8 9...152

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与OR4E04-1BM416C相关器件

型号	品牌	描述	获取价格	数据表
OR4E04-1BM416I	LATTICE	ORCASeries 4 FPGAs	获取价格
OR4E04-1BM680C	LATTICE	ORCASeries 4 FPGAs	获取价格
OR4E04-1BM680I	LATTICE	ORCASeries 4 FPGAs	获取价格
OR4E04-1BMN416C	LATTICE	Field Programmable Gate Array, 1296 CLBs, 333000 Gates, 420MHz, CMOS, PBGA416, PLASTIC, FB	获取价格
OR4E04-1BMN416I	LATTICE	Field Programmable Gate Array, 1296 CLBs, 333000 Gates, 420MHz, CMOS, PBGA416, PLASTIC, FB	获取价格
OR4E04-1BMN680C	LATTICE	Field Programmable Gate Array, 1296 CLBs, 333000 Gates, 420MHz, CMOS, PBGA680, PLASTIC, FB	获取价格

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