Datasheet > NTE4094BT

NTE4094BT

更新时间： 2024-11-03 19:51:03

品牌	Logo	应用领域
NTE		逻辑集成电路
页数	文件大小	规格书
5页	75K
描述
Serial In Parallel Out,

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技术参数
数据手册

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NTE4094BT 技术参数

生命周期：	Active	Reach Compliance Code：	unknown
风险等级：	2.17	逻辑集成电路类型：	SERIAL IN PARALLEL OUT
Base Number Matches：	1

NTE4094BT 数据手册

NTE4094B & NTE4094BT

Integrated Circuit

CMOS, 8−Stage Shift/Storage Register

Description:

The NTE4094B (16−Lead DIP) and NTE4094BT (SOIC−16) are 8−stage shift registers with a data latch

for each stage and a three−state output from each latch.

Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs.

The Q_Soutput data is for use in high−speed cascaded systems. The Q’_Soutput data is shifted on the

following negative clock transition for use in low−speed cascaded systems.

Data from each stage of the shift register is latched on the negative transition of the strobe input. Data

propagates through the latch while strobe is high.

Outputs of the eight data latches are controlled by three−state buffers which are placed in the high−im-

pedance state by a logic Low on Output Enable.

Features:

D Three−State Outputs

D Capable of Driving Two Low−Power TTL Loads, One Low−Power Schottky TTL Load or Two

HTL Loads Over the Rated Temperature Range

D Input Diode Protection

D Data Latch

D Dual Outputs for Data Out on Both Positive and Negative Clock Transitions

D Useful for Serial−to−Parallel Data Conversion

D Three−State Bus Compatible

Absolute Maximum Ratings: (Voltages Referenced to V_SS, Note 1)

DC Supply Voltage, V_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V

Input Voltage (All Inputs), V_in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V_DD+ 0.5V

DC Current Drain (Per Pin), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

Operating Temperature Range, T_A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55 to +125°C

Storage Temperature Range, T_stg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to +150°C

Note 1. These devices contain circuitry to protect the inputs against damage due to high static

voltages or electric fields; however, it is advised that normal precautions be taken to avoid

application of any voltage higher than maximum rated voltages to this high impedance cir-

cuit. For proper operation is is recommended that V_inand V_outbe constrained to the range

V_SS≤ (V_inor V_out) ≤ V_DD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V_SSor

V_DD).

12 3 4 5

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