Datasheet > NT256S64V8HC0G-8B

NT256S64V8HC0G-8B

更新时间： 2024-09-13 10:31:27

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
10页	143K
描述
32Mx64 bit Two Bank Unbuffered SDRAM Module

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中文翻译

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数据手册

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NT256S64V8HC0G

256MB : 32M x 64

Unbuffered SDRAM Module

32Mx64 bit Two Bank Unbuffered SDRAM Module

based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD

Features

168-Pin Unbuffered 8-Byte Dual In-Line Memory Module

Intended for PC133 applications

- Clock Frequency: 133MHz

Automatic and controlled Precharge commands

Programmable Operation:

- CAS Latency: 2, 3

- Clock Cycle: 7.5ns

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8

- Clock Assess Time: 5.4ns

Inputs and outputs are LVTTL (3.3V) compatible

Single 3.3V ± 0.3V Power Supply

Single Pulsed RAS interface

- Operation: Burst Read and Write or Multiple Burst Read with

Single Write

Suspend Mode and Power Down Mode

4096 Refresh cycles distributed across 64ms

Gold contacts

SDRAMs have 4 internal banks

Module has 2 physical bank

Fully Synchronous to positive Clock Edge

Data Mask for Byte Read/Write control

Auto Refresh (CBR) and Self Refresh

SDRAMs in TSOP Type II Package

Serial Presence Detect with Write Protect

Description

NT256S64V8HC0G is unbuffered 168-pin Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which is organized as 32Mx64

high-speed memory arrays and is configured as two 16M x 64 physical bank. The DIMM uses sixteen 16Mx8 SDRAMs in 400mil TSOP II

pack-ages. The DIMM achieves high-speed data transfer rates of up to 133MHz by employing a prefetch / pipeline hybrid architecture that

supports the JEDEC 1N rule while allowing very low burst power.

All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs.

All inputs are sampled at the positive edge of each externally supplied clock (CK0 - CK3). Internal operating modes are defined by combinations

, WE ,

, DQMB, and CKE0 – CKE1 signals. A command decoder initiates the necessary timings for each operation. A

RAS CAS

S0 S3

14-bit address bus accepts address information in a row / column multiplexing arrangement.

Prior to any Access operation, the

latency, burst type, burst length, and Burst operation type must be programmed into the DIMM by

CAS

address inputs A0-A9 during the Mode Register Set cycle. The DIMM uses serial presence detects implemented via a serial EEPROM using

the two-pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the

customer.

Ordering Information

Speed

Part Number

NT256S64V8HC0G-7K

NT256S64V8HC0G-75B

Organization

32Mx64

Leads

Gold

Power

3.3V

MHz.

t RCD

t RP

143MHz

133MHz

100MHz

125MHz

100MHz

NT256S64V8HC0G-8B

* CL = CAS Latency

Preliminary 10 / 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

12 3 4 5 6 7...10

中文翻译

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与NT256S64V8HC0G-8B相关器件

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NT256S72V89A0G	ETC	获取价格	32Mx72 bit One Bank Unbuffered SDRAM Module
NT256S72V89A0G-75B	ETC	获取价格	32Mx72 bit One Bank Unbuffered SDRAM Module
NT256S72V89A0G-7K	ETC	获取价格	32Mx72 bit One Bank Unbuffered SDRAM Module
NT256S72V89A0G-8B	ETC	获取价格	32Mx72 bit One Bank Unbuffered SDRAM Module
NT2907	NEC	获取价格	Small Signal Bipolar Transistor, 0.6A I(C), 40V V(BR)CEO, 1-Element, PNP, Silicon, TO-92,
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NT2A	TTELEC	获取价格	Semi-precision non-inductive power wirewound resistor
NT2A69	TTELEC	获取价格	Semi-precision non-inductive power wirewound resistor
NT2B79	TTELEC	获取价格	Semi-precision non-inductive power wirewound resistor
NT2CHP	VISHAY	获取价格	Transistor

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