Datasheet > NT256S72V89A0G-7K

NT256S72V89A0G-7K

更新时间： 2024-09-13 10:31:27

品牌	Logo	应用领域
其他 - ETC		内存集成电路动态存储器时钟
页数	文件大小	规格书
12页	164K
描述
32Mx72 bit One Bank Unbuffered SDRAM Module

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NT256S72V89A0G

256MB : 32M x 72

Unbuffered SDRAM Module

32Mx72 bit One Bank Unbuffered SDRAM Module

based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD

Features

168-Pin Unbuffered 8-Byte Dual In-Line Memory Module

Intended for PC133 applications

- Clock Frequency: 133MHz

Automatic and controlled Precharge commands

Programmable Operation:

- CAS Latency: 2, 3

- Clock Cycle: 7.5ns

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8

- Clock Assess Time: 5.4ns

Inputs and outputs are LVTTL (3.3V) compatible

Single 3.3V ± 0.3V Power Supply

Single Pulsed RAS interface

- Operation: Burst Read and Write or Multiple Burst Read with

Single Write

Suspend Mode and Power Down Mode

8192 Refresh cycles distributed across 64ms

Gold contacts

SDRAMs have 4 internal banks

Module has 1 physical bank

Fully Synchronous to positive Clock Edge

Data Mask for Byte Read/Write control

Auto Refresh (CBR) and Self Refresh

SDRAMs in TSOP Type II Package

Serial Presence Detect with Write Protect

Description

NT256S72V89A0G is unbuffered 168-pin Synchronous DRAM Dual In-Line Memory Modules (DIMM) which is organized as 32Mx72

high-speed memory arrays and is configured as one 32M x 72 physical bank. The DIMM uses nine 32Mx8 SDRAMs in 400mil TSOP II

packages. The DIMM achieves high-speed data transfer rates of up to 133MHz by employing a prefetch / pipeline hybrid architecture that

supports the JEDEC 1N rule while allowing very low burst power.

All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs.

All inputs are sampled at the positive edge of each externally supplied clock (CK0, CK2). Internal operating modes are defined by combinations

, WE ,

, DQMB, and CKE0 signals. A command decoder initiates the necessary timings for each operation. A 15-bit

RAS CAS

S0 S2

address bus accepts address information in a row / column multiplexing arrangement.

Prior to any Access operation, the

latency, burst type, burst length, and Burst operation type must be programmed into the DIMM by

CAS

address inputs A0-A9 during the Mode Register Set cycle. The DIMM uses serial presence detects implemented via a serial EEPROM using

the two-pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the

customer.

Ordering Information

Speed

Part Number

Organization

Leads

Gold

Power

3.3V

MHz.

t RCD

t RP

143MHz

133MHz

100MHz

125MHz

100MHz

NT256S72V89A0G-7K

NT256S72V89A0G-75B

32Mx72

NT256S72V89A0G-8B

* CL = CAS Latency

Preliminary 09 / 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

12 3 4 5 6 7...12

中文翻译

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与NT256S72V89A0G-7K相关器件

型号	品牌	获取价格	描述	数据表
NT256S72V89A0G-8B	ETC	获取价格	32Mx72 bit One Bank Unbuffered SDRAM Module
NT2907	NEC	获取价格	Small Signal Bipolar Transistor, 0.6A I(C), 40V V(BR)CEO, 1-Element, PNP, Silicon, TO-92,
NT2907A	NEC	获取价格	Small Signal Bipolar Transistor, 0.6A I(C), 60V V(BR)CEO, 1-Element, PNP, Silicon, TO-92,
NT2A	TTELEC	获取价格	Semi-precision non-inductive power wirewound resistor
NT2A69	TTELEC	获取价格	Semi-precision non-inductive power wirewound resistor
NT2B79	TTELEC	获取价格	Semi-precision non-inductive power wirewound resistor
NT2CHP	VISHAY	获取价格	Transistor
NT2CHP-2	VISHAY	获取价格	Small Signal Field-Effect Transistor, 1-Element, N-Channel, Silicon, Junction FET
NT2H1001	NXP	获取价格	NTAG 210Î¼, NFC Forum Type 2 Tag compliant IC
NT2H1001G0DUD	NXP	获取价格	NTAG 210Î¼, NFC Forum Type 2 Tag compliant IC

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