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NS32FX100VF-15 PDF预览

NS32FX100VF-15

更新时间: 2024-09-17 21:19:39
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
94页 948K
描述
IC MULTIFUNCTION PERIPHERAL, PQFP132, PLASTIC, QFP-132, Multifunction Peripheral

NS32FX100VF-15 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:BQFP, SPQFP132,1.2SQReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
地址总线宽度:24边界扫描:NO
总线兼容性:NS32FX161; NS32FV16; NS32FX164最大时钟频率:15.15 MHz
外部数据总线宽度:16JESD-30 代码:S-PQFP-G132
JESD-609代码:e0长度:24.13 mm
I/O 线路数量:24串行 I/O 数:2
端子数量:132最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:BQFP封装等效代码:SPQFP132,1.2SQ
封装形状:SQUARE封装形式:FLATPACK, BUMPER
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:4.45 mm
子类别:Multifunction Peripherals最大压摆率:170 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:MOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.64 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:24.13 mm
uPs/uCs/外围集成电路类型:MULTIFUNCTION PERIPHERALBase Number Matches:1

NS32FX100VF-15 数据手册

 浏览型号NS32FX100VF-15的Datasheet PDF文件第2页浏览型号NS32FX100VF-15的Datasheet PDF文件第3页浏览型号NS32FX100VF-15的Datasheet PDF文件第4页浏览型号NS32FX100VF-15的Datasheet PDF文件第5页浏览型号NS32FX100VF-15的Datasheet PDF文件第6页浏览型号NS32FX100VF-15的Datasheet PDF文件第7页 
PRELIMINARY  
July 1992  
NS32FX100-15/NS32FX100-20/NS32FV100-20/  
NS32FV100-25/NS32FX200-20/NS32FX200-25  
System Controller  
Y
Programmable wait state generator  
General Description  
Y
Y
Demultiplexed address and data buses  
Multiplexed DRAM address bus (NS32FX200 and  
NS32FV100)  
The NS32FX200, NS32FV100 and NS32FX100 are highly  
integrated system chips designed for a FAX system based  
on National Semiconductor’s embedded processorsÐ  
NS32FX161, NS32FV16 or NS32FX164. The NS32FX100 is  
the common core for all three system chips. The  
NS32FV100 and NS32FX200 offer additional functions.  
Throughout this document, references to the NS32FX100  
also apply to both the NS32FV100 and the NS32FX200.  
Specific NS32FV100 or NS32FX200 features are explicitly  
indicated.  
Y
Y
Y
Supports 3V freeze mode by maintaining only elapsed  
time counter  
Control of power consumption by disabling inactive  
modules and reducing the clock frequency  
Operating frequency  
Ð Normal mode: 19.6608 MHzÐ24.576 MHz in steps  
of 1.2288 MHz. (NS32FX200)  
Ð Normal mode: 19.6608 MHzÐ24.576 MHz in steps  
of 1.2288 MHz. (NS32FV100)  
Ð Normal mode: 14.7456 MHzÐ19.6608 MHz in steps  
of 1.2288 MHz. (NS32FX100)  
Ð Power Save mode: Normal mode frequency divided  
by sixteen  
The NS32FX200, NS32FV100 and NS32FX100 feature an  
interface to devices like stepper motors, printers and scan-  
ners, a Sigma-Delta CODEC, an elapsed-time counter, a  
DMA controller, an interrupt controller, and a UART.  
The NS32FX200 is optimized for high-end FAX applications,  
such as plain-paper FAX and multifunctional peripherals.  
The NS32FX100, is optimized for low-cost FAX applica-  
tions. The NS32FV100 is optimized for thermal paper FAX  
machines with Digital Answering Machine support.  
Y
On-Chip full duplex Sigma-Delta CODEC with:  
b
Ð Total harmonic distortion better than 70 dB  
Ð Programmable hybrid balance filter  
Ð Programmable reception and transmission filters  
Ð Programmable gain control  
Features  
Y
Y
Y
On-Chip Interrupt Control Unit with:  
Ð 16 interrupt sources  
Ð Programmable triggering mode  
On-Chip counters, WATCHDOGTM, UART,  
MICROWIRETM, System Clock Generator, and I/O  
ports  
Direct interface to the NS32FX161, NS32FV16 and  
NS32FX164 embedded processors  
Y
Supports a variety of Contact Image Sensor (CIS) and  
Charge Coupled Device (CCD) scanners  
Y
Direct interface to  
a variety of Thermal Print Head  
(TPH) printers. Bitmap shifter and DMA channels facili-  
tate the connection of other types of printers  
Supports two stepper motors  
Y
Y
On-Chip DMA controller (NS32FX200Ðfour channels,  
NS32FX100, NS32FV100Ðthree channels)  
Up to 37 on-chip general purpose I/O pins, expandable  
externally  
Y
Y
Direct interface to ROM and SRAM. The NS32FX200  
and NS32FV100, in addition, interface to DRAM  
devices  
Y
Y
Flexible allocation of I/O and modules’ pins  
132-pin JEDEC PQFP package  
TL/EE/11331–1  
FIGURE 1-1. A FAX Controller Block Diagram  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
MICROWIRETM and WATCHDOGTM are trademarks of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/EE11331  
RRD-B30M105/Printed in U. S. A.  

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16-BIT, 30.3MHz, MIXED DSP, PQCC68, PLASTIC, LCC-68