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NS32491A

更新时间： 2024-09-24 23:54:27

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
12页	193K
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NS32491A 数据手册

July 1993

DP8391A/NS32491A SNI Serial Network Interface

10 Mb/s Manchester encoding/decoding with receive

clock recovery

General Description

The DP8391A Serial Network Interface (SNI) provides the

Manchester data encoding and decoding functions for

IEEE 802.3 Ethernet/Cheapernet type local area networks.

The SNI interfaces the DP8390 Network Interface Controller

(NIC) to the Ethernet transceiver cable. When transmitting,

the SNI converts non-return-to-zero (NRZ) data from the

controller and clock pulses into Manchester encoding and

sends the converted data differentially to the transceiver.

The opposite process occurs on the receive path, where a

digital phase-locked loop decodes 10 Mbit/s signals with as

Patented digital phase locked loop (DPLL) decoder re-

quires no precision external components

Decodes Manchester data with up to 18 ns of jitter

Loopback capability for diagnostics

Externally selectable half or full step modes of opera-

tion at transmit output

Squelch circuits at the receive and collision inputs re-

ject noise

High voltage protection at transceiver interface (16V)

TTL/MOS compatible controller interface

Connects directly to the transceiver (AUI) cable

much as 18 ns of jitter.

The DP8391A SNI is a functionally complete Manchester

encoder/decoder including ECL like balanced driver and re-

ceivers, on board crystal oscillator, collision signal transla-

tor, and a diagnostic loopback circuit.

Table of Contents

1.0 System Diagram

The SNI is part of a three chip set that implements the com-

plete IEEE compatible network node electronics as shown

below. The other two chips are the DP8392 Coax Transceiv-

er Interface (CTI) and the DP8390 Network Interface Con-

troller (NIC).

2.0 Block Diagram

3.0 Functional Description

3.1

3.2

3.3

3.4

3.5

Oscillator

Encoder

Incorporated into the CTI are the transceiver, collision and

jabber functions. The Media Access Protocol and the buffer

management tasks are performed by the NIC. There is an

isolation requirement on signal and power lines between the

CTI and the SNI. This is usually accomplished by using a set

of miniature pulse transformers that come in a 16-pin plastic

DIP for signal lines. Power isolation, however, is done by

using a DC to DC converter.

Decoder

Collision Translator

Loopback

4.0 Connection Diagrams

5.0 Pin Descriptions

6.0 Absolute Maximum Ratings

7.0 Electrical Characteristics

8.0 Switching Characteristics

9.0 Timing and Load Diagrams

10.0 Physical Dimensions

Features

Compatible with Ethernet II, IEEE 802.3; 10Base5,

10Base2, and 10Base-T

1.0 System Diagram

IEEE 802.3 Compatible Ethernet/Cheapernet Local Area Network Chip Set

TL/F/9357–1

1995 National Semiconductor Corporation

TL/F/9357

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7...12

中文翻译

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与NS32491A相关器件

型号	品牌	获取价格	描述	数据表
NS32491AN	TI	获取价格	DATACOM, ETHERNET TRANSCEIVER, PDIP24, 0.300 INCH, PLASTIC, DIP-24
NS32491AV	TI	获取价格	DATACOM, ETHERNET TRANSCEIVER, PQCC28, PLASTIC, LCC-28
NS32491AVX	TI	获取价格	DATACOM, ETHERNET TRANSCEIVER, PQCC28, PLASTIC, CC-28
NS32491AV-X	TI	获取价格	DATACOM, ETHERNET TRANSCEIVER, PQCC28, PLASTIC, LCC-28
NS32492B	NSC	获取价格	Coaxial Transceiver Interface
NS32532-20	ETC	获取价格
NS32532-25	ETC	获取价格
NS32532-30	ETC	获取价格
NS32580-20	TI	获取价格	SPECIALTY MICROPROCESSOR CIRCUIT, CPGA172, CAVITY DOWN, PGA-172
NS32580-25	TI	获取价格	SPECIALTY MICROPROCESSOR CIRCUIT, CPGA172, CAVITY DOWN, PGA-172

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