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NS32532-25 PDF预览

NS32532-25

更新时间: 2024-01-16 12:48:36
品牌 Logo 应用领域
其他 - ETC 外围集成电路时钟
页数 文件大小 规格书
102页 1116K
描述

NS32532-25 技术参数

生命周期:Obsolete包装说明:PGA,
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.84
地址总线宽度:32位大小:32
边界扫描:NO最大时钟频率:50 MHz
外部数据总线宽度:32格式:FLOATING POINT
集成缓存:NOJESD-30 代码:S-CPGA-P175
低功率模式:NO端子数量:175
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified座面最大高度:4.699 mm
速度:25 MHz最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:NO技术:CMOS
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULARuPs/uCs/外围集成电路类型:MICROPROCESSOR
Base Number Matches:1

NS32532-25 数据手册

 浏览型号NS32532-25的Datasheet PDF文件第2页浏览型号NS32532-25的Datasheet PDF文件第3页浏览型号NS32532-25的Datasheet PDF文件第4页浏览型号NS32532-25的Datasheet PDF文件第5页浏览型号NS32532-25的Datasheet PDF文件第6页浏览型号NS32532-25的Datasheet PDF文件第7页 
May 1991  
NS32532-20/NS32532-25/NS32532-30  
High-Performance 32-Bit Microprocessor  
General Description  
The NS32532 is a high-performance 32-bit microprocessor  
Features  
Y
Software compatible with the Series 32000 family  
32-bit architecture and implementation  
4-GByte uniform addressing space  
On-chip memory management unit with 64-entry  
translation look-aside buffer  
Y
Y
Y
in the Series 32000 family. It is software compatible with  
É
the previous microprocessors in the family but with a greatly  
enhanced internal implementation.  
The high-performance specifications are the result of a four-  
stage instruction pipeline, on-chip instruction and data  
caches, on-chip memory management unit and a signifi-  
cantly increased clock frequency. In addition, the system  
interface provides optimal support for applications spanning  
a wide range, from low-cost, real-time controllers to highly  
sophisticated, general purpose multiprocessor systems.  
Y
Y
Y
Y
4-Stage instruction pipeline  
512-Byte on-chip instruction cache  
1024-Byte on-chip data cache  
High-performance bus  
Ð Separate 32-bit address and data lines  
Ð Burst mode memory accessing  
Ð Dynamic bus sizing  
The NS32532 integrates more than 370,000 transistors fab-  
ricated in a 1.25 mm double-metal CMOS technology. The  
advanced technology and mainframe-like design of the de-  
vice enable it to achieve more than 10 times the throughput  
of the NS32032 in typical applications.  
Y
Y
Y
Y
Extensive multiprocessing support  
Floating-point support via the NS32381 or NS32580  
1.25 mm double-metal CMOS technology  
175-pin PGA package  
In addition to generally improved performance, the  
NS32532 offers much faster interrupt service and task  
switching for real-time applications.  
Block Diagram  
TL/EE/9354–1  
FIGURE 1  
Series 32000É and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/EE/9354  
RRD-B30M105/Printed in U. S. A.  

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