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NM27C512VE120X PDF预览

NM27C512VE120X

更新时间: 2024-09-29 13:11:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 存储内存集成电路可编程只读存储器OTP只读存储器电动程控只读存储器
页数 文件大小 规格书
10页 109K
描述
OTP ROM, 64KX8, 120ns, CMOS, PQCC32, PLASTIC, LCC-32

NM27C512VE120X 技术参数

生命周期:Obsolete零件包装代码:QFJ
包装说明:QCCJ,针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.21
最长访问时间:120 nsJESD-30 代码:R-PQCC-J32
长度:13.995 mm内存密度:524288 bit
内存集成电路类型:OTP ROM内存宽度:8
功能数量:1端子数量:32
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:64KX8
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:3.56 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:11.455 mmBase Number Matches:1

NM27C512VE120X 数据手册

 浏览型号NM27C512VE120X的Datasheet PDF文件第2页浏览型号NM27C512VE120X的Datasheet PDF文件第3页浏览型号NM27C512VE120X的Datasheet PDF文件第4页浏览型号NM27C512VE120X的Datasheet PDF文件第5页浏览型号NM27C512VE120X的Datasheet PDF文件第6页浏览型号NM27C512VE120X的Datasheet PDF文件第7页 
July 1998  
NM27C512  
524,288-Bit (64K x 8) High Performance CMOS EPROM  
The NM27C512 is one member of a high density EPROM Family  
which range in densities up to 4 Megabit.  
General Description  
The NM27C512 is a high performance 512K UV Erasable Electri-  
cally Programmable Read Only Memory (EPROM). It is manufac-  
tured using Fairchild’s proprietary CMOS AMG™ EPROM tech-  
nology for an excellent combination of speed and economy while  
providing excellent reliability.  
Features  
High performance CMOS  
— 90 ns access time  
Fast turn-off for microprocessor compatibility  
TheNM27C512providesmicroprocessor-basedsystemsstorage  
capacity for portions of operating system and application soft-  
Manufacturers identification code  
ware. Its 90 ns access time provides no wait-state operation with  
high-performance CPUs. The NM27C512 offers a single chip  
solution for the code storage requirements of 100% firmware-  
based equipment. Frequently-used software routines are quickly  
executed from EPROM storage, greatly enhancing system utility.  
JEDEC standard pin configuration  
— 28-pin PDIP package  
— 32-pin chip carrier  
— 28-pin CERDIP package  
The NM27C512 is configured in the standard JEDEC EPROM  
pinoutwhichprovidesaneasyupgradepathforsystemswhichare  
currently using standard EPROMs.  
Block Diagram  
Data Outputs O - O  
0
7
V
CC  
GND  
V
PP  
OE  
Output Enable and  
Chip Enable Logic  
CE/PGM  
Output  
Buffers  
Y Decoder  
524,288-Bit  
Cell Matrix  
A
- A  
15  
0
Address  
Inputs  
X Decoder  
DS010834-1  
AMG is a trademark of WSI, Inc.  
1
© 1998 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  

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