5秒后页面跳转
NLX3G14FMUTCG PDF预览

NLX3G14FMUTCG

更新时间: 2024-11-07 01:18:27
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
8页 76K
描述
Triple Schmitt-Trigger Inverter

NLX3G14FMUTCG 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:DFN包装说明:1.45 X 1 MM, 0.35 MM PITCH, LEAD FREE, UDFN-8
针数:8Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:14 weeks
风险等级:1.59系列:3G
JESD-30 代码:R-PDSO-N8JESD-609代码:e4
长度:1.45 mm负载电容(CL):15 pF
逻辑集成电路类型:INVERTER最大I(ol):0.008 A
湿度敏感等级:1功能数量:3
输入次数:1端子数量:8
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装等效代码:SOLCC8,.04,14封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE包装方法:TAPE AND REEL
电源:1.8/5 VProp。Delay @ Nom-Sup:9.1 ns
传播延迟(tpd):9.1 ns认证状态:Not Qualified
施密特触发器:YES座面最大高度:0.55 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):2.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.35 mm
端子位置:DUAL宽度:1 mm
Base Number Matches:1

NLX3G14FMUTCG 数据手册

 浏览型号NLX3G14FMUTCG的Datasheet PDF文件第2页浏览型号NLX3G14FMUTCG的Datasheet PDF文件第3页浏览型号NLX3G14FMUTCG的Datasheet PDF文件第4页浏览型号NLX3G14FMUTCG的Datasheet PDF文件第5页浏览型号NLX3G14FMUTCG的Datasheet PDF文件第6页浏览型号NLX3G14FMUTCG的Datasheet PDF文件第7页 
NLX3G14  
Triple Schmitt-Trigger  
Inverter  
The NLX3G14 MiniGatet is an advanced high−speed CMOS  
triple Schmitt−trigger inverter in ultra−small footprint.  
The NLX3G14 input and output structures provide protection when  
voltages up to 7.0 V are applied, regardless of the supply voltage.  
The NLX3G14 can be used to enhance noise immunity or to square  
up slowly changing waveforms.  
www.onsemi.com  
MARKING  
DIAGRAMS  
Features  
UDFN8  
1.45 x 1.0  
CASE 517BZ  
Designed for 1.65 V to 5.5 V V Operation  
CC  
2 M  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
1
24 Balanced Output Source and Sink Capability  
Balanced Propagation Delays  
UDFN8  
1.6 x 1.0  
CASE 517BY  
Overvoltage Tolerant (OVT) Input and Output Pins  
Ultra−Small Packages  
X M  
X M  
1
These are Pb−Free Devices  
UDFN8  
1.95 x 1.0  
CASE 517CA  
1
IN A1  
OUT Y3  
IN A2  
1
2
3
4
8
7
6
5
V
CC  
F, AC, 2 = Specific Device Code  
M
= Date Code  
OUT Y1  
IN A3  
G
= Pb−Free Package  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
GND  
OUT Y2  
Figure 1. Pinout (Top View)  
1
IN A1  
IN A2  
IN A3  
OUT Y1  
OUT Y2  
OUT Y3  
1
1
PIN ASSIGNMENT  
Figure 2. Logic Symbol  
1
2
3
4
5
6
7
8
IN A1  
OUT Y3  
IN A2  
GND  
OUT Y2  
FUNCTION TABLE  
A
Y
IN A3  
OUT Y1  
L
H
H
L
V
CC  
© Semiconductor Components Industries, LLC, 2016  
1
Publication Order Number:  
July, 2016 − Rev. 3  
NLX3G14/D  

与NLX3G14FMUTCG相关器件

型号 品牌 获取价格 描述 数据表
NLX3G16 ONSEMI

获取价格

Triple Non-Inverting Buffer
NLX3G16_16 ONSEMI

获取价格

Triple Non-Inverting Buffer
NLX3G16AMX1TCG ONSEMI

获取价格

Triple Non-Inverting Buffer
NLX3G16BMX1TCG ONSEMI

获取价格

Triple Non-Inverting Buffer
NLX3G16CMX1TCG ONSEMI

获取价格

Triple Non-Inverting Buffer
NLX3G16DMUTCG ONSEMI

获取价格

Triple Non-Inverting Buffer
NLX3G16EMUTCG ONSEMI

获取价格

Triple Non-Inverting Buffer
NLX3G16FMUTCG ONSEMI

获取价格

Triple Non-Inverting Buffer
NLX3G17 ONSEMI

获取价格

Triple Non-Inverting Schmitt-Trigger Buffer
NLX3G17AMX1TCG ONSEMI

获取价格

Triple Non-Inverting Schmitt-Trigger Buffer