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NLX3G16BMX1TCG PDF预览

NLX3G16BMX1TCG

更新时间: 2024-11-05 06:00:59
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 113K
描述
Triple Non-Inverting Buffer

NLX3G16BMX1TCG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:LGA包装说明:1.60 X 1 MM, 0.40 MM PITCH, LEAD FREE, ULLGA-8
针数:8Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.71
系列:HCJESD-30 代码:R-XDSO-N8
JESD-609代码:e4长度:1.6 mm
负载电容(CL):15 pF逻辑集成电路类型:BUFFER
最大I(ol):0.004 A湿度敏感等级:1
功能数量:3输入次数:1
端子数量:8最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:UNSPECIFIED
封装代码:VSON封装等效代码:SOLCC6,.04,16
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:1.8/5 V
Prop。Delay @ Nom-Sup:12 ns传播延迟(tpd):12 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:0.4 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.4 mm端子位置:DUAL
宽度:1 mmBase Number Matches:1

NLX3G16BMX1TCG 数据手册

 浏览型号NLX3G16BMX1TCG的Datasheet PDF文件第2页浏览型号NLX3G16BMX1TCG的Datasheet PDF文件第3页浏览型号NLX3G16BMX1TCG的Datasheet PDF文件第4页浏览型号NLX3G16BMX1TCG的Datasheet PDF文件第5页浏览型号NLX3G16BMX1TCG的Datasheet PDF文件第6页浏览型号NLX3G16BMX1TCG的Datasheet PDF文件第7页 
NLX3G16  
Triple Non-Inverting Buffer  
The NLX3G16 MiniGatet is an advanced highspeed CMOS  
triple noninverting buffer in ultrasmall footprint.  
The NLX3G16 input and output structures provide protection when  
voltages up to 7.0 V are applied, regardless of the supply voltage.  
http://onsemi.com  
MARKING  
Features  
High Speed: t = 1.8 ns (Typ) @ V = 5.0 V  
PD  
CC  
Designed for 1.65 V to 5.5 V V Operation  
CC  
DIAGRAMS  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
ULLGA8  
1.45 x 1.0  
24 mA Balanced Output Source and Sink Capability  
Balanced Propagation Delays  
JM  
CASE 613AA  
1
Overvoltage Tolerant (OVT) Input and Output Pins  
UltraSmall Packages  
ULLGA8  
1.6 x 1.0  
CASE 613AB  
ADM  
G
These are PbFree Devices  
1
ULLGA8  
1.95 x 1.0  
CASE 613AC  
ADM  
G
IN A1  
OUT Y3  
IN A2  
1
2
3
4
8
7
6
5
V
CC  
1
OUT Y1  
IN A3  
J or AD = Specific Device Code  
M
G
= Date Code  
= PbFree Package  
PIN ASSIGNMENT  
IN A1  
GND  
OUT Y2  
1
2
3
4
5
6
7
8
OUT Y3  
Figure 1. Pinout (Top View)  
IN A2  
GND  
1
OUT Y2  
IN A1  
OUT Y1  
OUT Y2  
OUT Y3  
IN A3  
1
1
IN A2  
IN A3  
OUT Y1  
V
CC  
FUNCTION TABLE  
Figure 2. Logic Symbol  
A
Y
L
L
H
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
© Semiconductor Components Industries, LLC, 2008  
1
Publication Order Number:  
November, 2008 Rev. 0  
NLX3G16/D  

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