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NLSX5012

更新时间： 2024-11-02 10:25:47
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器
页数 文件大小 规格书
14页 159K
描述
2-Bit 100 Mb/s Configurable Dual-Supply Level Translator

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NLSX5012 数据手册

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NLSX5012  
2-Bit 100 Mb/s Configurable  
Dual-Supply Level  
Translator  
The NLSX5012 is a 2-bit configurable dual-supply autosensing  
bidirectional level translator that does not require a direction control  
http://onsemi.com  
MARKING  
pin. The I/O V - and I/O V -ports are designed to track two  
CC  
L
different power supply rails, V and V respectively. Both the V  
CC  
L
CC  
DIAGRAMS  
and the V supply rails are configurable from 0.9 V to 4.5 V. This  
L
allows a logic signal on the V side to be translated to either a higher  
L
UDFN8  
MU SUFFIX  
CASE 517AJ  
8
AE M  
G
or a lower logic signal voltage on the V side, and vice-versa.  
CC  
The NLSX5012 offers the feature that the values of the V and  
1
CC  
V
supplies are independent. Design flexibility is maximized  
L
VA = Specific Device Code  
because V can be set to a value either greater than or less than the  
L
M
= Date Code  
V
supply. In contrast, the majority of competitive auto sense  
G
= Pb−Free Package  
CC  
translators have a restriction that the value of the V supply must be  
L
8
equal to less than (V - 0.4) V.  
CC  
SX5012  
ALYWG  
G
SO−8  
D SUFFIX  
CASE 751  
The NLSX5012 has high output current capability, which allows  
the translator to drive high capacitive loads such as most high  
frequency EMI filters. Another feature of the NLSX5012 is that each  
8
1
1
I/O_V and I/O_V  
output.  
channel can function as either an input or an  
Ln  
CCn  
A
L
= Assembly Location  
= Wafer Lot  
An Output Enable (EN) input is available to reduce the power  
consumption. The EN pin can be used to disable both I/O ports by  
putting them in 3-state which significantly reduces the supply current  
Y
W
G
= Year  
= Work Week  
= Pb−Free Package  
from both V and V . The EN signal is referenced to the V supply.  
CC  
L
L
8
Micro8  
DM SUFFIX  
CASE 846A  
Features  
5012  
AYWG  
G
• Wide V , V Operating Range: 0.9 V to 4.5 V  
CC  
L
1
• V and V are independent  
L
CC  
1
− V may be greater than, equal to, or less than V  
L
CC  
A
= Assembly Location  
= Year  
= Work Week  
• High 100 pF Capacitive Drive Capability  
Y
W
G
• High−Speed with 140 Mb/s Guaranteed Date Rate  
= Pb−Free Package  
for V , V > 1.8 V  
CC  
L
• Low Bit−to−Bit Skew  
• Overvoltage Tolerant Enable and I/O Pins  
• Non−preferential Power−Up Sequencing  
• Power−Off Protection  
• Small packaging: UDFN8, SO−8, Micro8  
• These are Pb−Free Devices  
ORDERING INFORMATION  
†
Device  
Package  
Shipping  
NLSX5012MUTAG  
NLSX5012DR2G  
NLSX5012DMR2G  
UDFN8 3000/Tape & Reel  
(Pb−Free)  
SO−8  
(Pb−Free)  
2500/Tape & Reel  
4000/Tape & Reel  
Typical Applications  
• Mobile Phones, PDAs, Other Portable Devices  
Micro8  
(Pb−Free)  
Important Information  
• ESD Protection for All Pins:  
♦ HBM (Human Body Model) > 8000 V  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
©
Semiconductor Components Industries, LLC, 2010  
1
Publication Order Number:  
June, 2010 − Rev. 1  
NLSX5012/D  
1234567...14

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