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NLAS1053_06 PDF预览

NLAS1053_06

更新时间: 2024-11-02 03:46:23
品牌 Logo 应用领域
安森美 - ONSEMI 解复用器开关
页数 文件大小 规格书
10页 121K
描述
2:1 Mux/Demux Analog Switches

NLAS1053_06 数据手册

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NLAS1053  
2:1 Mux/Demux Analog  
Switches  
The NLAS1053 is an advanced CMOS analog switch fabricated  
with silicon gate CMOS technology. It achieves very high speed  
propagation delays and low ON resistances while maintaining CMOS  
low power dissipation. The device consists of a single 2:1  
Mux/Demux (SPDT), similar to ON Semiconductor’s NLAS4053  
analog and digital voltages that may vary across the full power supply  
http://onsemi.com  
US8  
range (from V to GND).  
CC  
The inhibit and select input pins have over voltage protection that  
US SUFFIX  
CASE 493−01  
allows voltages above V up to 7.0 V to be present without damage  
CC  
1
or disruption of operation of the part, regardless of the operating  
voltage.  
MARKING DIAGRAMS  
Features  
High Speed: t = 1 ns (Typ) at V = 5.0 V  
PD  
CC  
8
Low Power Dissipation: I = 2 A (Max) at T = 25°C  
CC  
A
High Bandwidth, Improved Linearity, and Low RDS  
ON  
AC M G  
G
INH Pin Allows a Both Channels ‘OFF’ Condition (With a High)  
RDS 25 , Performance Very Similar to the NLAS4053  
ON  
1
Break Before Make Circuitry, Prevents Inadvertent Shorts  
Useful For Switching Video Frequencies Beyond 50 MHz  
Latchup Performance Exceeds 300 mA  
AC = Specific Device Code  
M
G
= Date Code*  
= Pb−Free Package  
ESD Performance: HBM > 2000 V; MM > 200 V, CDM > 1500 V  
Tiny US8 Package, Only 2.1 X 3.0 mm  
Pb−Free Package is Available  
(Note: Microdot may be in either location)  
*Date Code orientation may vary depending  
upon manufacturing location.  
ORDERING INFORMATION  
Device  
Package  
Shipping  
NLAS1053US  
US8  
3000 / Tape & Reel  
NLAS1053USG  
US8  
(Pb−Free)  
3000 / Tape & Reel  
COM  
1
2
3
4
V
8
7
6
5
CC  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specifications  
Brochure, BRD8011/D.  
INH  
N/C  
CH0  
CH1  
GND  
Select  
FUNCTION TABLE  
INH  
Select  
Ch 0  
Ch 1  
Figure 1. Pin Assignment  
H
L
L
X
L
OFF  
ON  
OFF  
OFF  
ON  
H
OFF  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
May, 2006 − Rev. 2  
NLAS1053/D  

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