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NL17SV00XV5T2 PDF预览

NL17SV00XV5T2

更新时间: 2024-01-17 16:34:37
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
6页 45K
描述
Single 2-Input NAND Gate

NL17SV00XV5T2 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:SOT包装说明:1.60 X 1.60 MM, 0.60 MM HEIGHT, ROHS COMPLIANT, SOT-553, 5 PIN
针数:5Reach Compliance Code:unknown
风险等级:5.83系列:AUP/ULP/V
JESD-30 代码:R-PDSO-F5JESD-609代码:e3
长度:1.6 mm逻辑集成电路类型:NAND GATE
湿度敏感等级:NOT SPECIFIED功能数量:1
输入次数:2端子数量:5
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSOF
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):9.9 ns
认证状态:COMMERCIAL座面最大高度:0.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.9 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:FLAT端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:1.2 mm

NL17SV00XV5T2 数据手册

 浏览型号NL17SV00XV5T2的Datasheet PDF文件第2页浏览型号NL17SV00XV5T2的Datasheet PDF文件第3页浏览型号NL17SV00XV5T2的Datasheet PDF文件第4页浏览型号NL17SV00XV5T2的Datasheet PDF文件第5页浏览型号NL17SV00XV5T2的Datasheet PDF文件第6页 
NL17SV00XV5T2  
Single 2−Input NAND Gate  
The NL17SV00 is an ultra−high performance 2−Input NAND gate  
manufactured in 0.35 mm technology, with excellent performance  
down to 0.9 V. This device is ideal for extremely high speed and  
high−drive applications. Additionally, limitations of board space are  
no longer a constraint. The very small SOT−553 makes this device fit  
most tight designs and spaces.  
http://onsemi.com  
MARKING  
Features  
Extremely High Speed: 1.0 ns (Typ) @ V = 3.3 V  
CC  
Designed for 0.9 to 3.3 V Operation  
Overvoltage Tolerance (OVT)* Input Pins Permits Logic Translation  
DIAGRAM  
5
Balanced "24 mA Output Drive @ V 3.3 V  
1
CC  
Near Zero Static Supply Current  
Ultra−Tiny SOT−553 5−Pin Package, only 1.6 x 1.6 x 0.6 mm  
All Devices in Package SOT−553 are Inherently Pb−Free**  
UH D  
SOT−553  
CASE 463B  
UH = Specific Device Code  
D
= Date Code  
Typical Applications  
Cellular  
PIN DIAGRAM  
Digital Camera  
PDA  
Digital Video  
5
4
IN B  
1
2
3
V
CC  
Industry Leadership  
IN A  
Functionally Similar to NC7SV00 and SN74AUC1G00  
GND  
OUT Y  
IN A  
&
OUT Y  
PIN ASSIGNMENT  
IN B  
PIN #  
FUNCTION  
Figure 1. Logic Symbol  
1
2
3
4
5
IN B  
IN A  
FUNCTION TABLE  
GND  
OUT Y  
Inputs  
B
Output  
Y
A
V
CC  
L
L
L
H
L
H
H
H
L
ORDERING INFORMATION  
H
H
H
Device  
Package  
Shipping†  
NL17SV00XV5T2 SOT−553  
(Pb−Free)  
4000 Tape & Reel  
(178 mm)  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specifications  
Brochure, BRD8011/D.  
*Overvoltage Tolerance (OVT) enables input pins to function outside (higher) of  
their operating voltages, with no damage to the devices or to signal integrity.  
**For additional information on our Pb−Free strategy and soldering details,  
please download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
January, 2005 − Rev. 2  
NL17SV00XV5T2/D  

NL17SV00XV5T2 替代型号

型号 品牌 替代类型 描述 数据表
NL17SV00XV5T2G ONSEMI

完全替代

Single 2-Input NAND Gate
SN74AUC1G00DRLRG4 TI

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