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NCP5393AMNR2G

更新时间： 2024-11-08 05:52:03
品牌 Logo 应用领域
安森美 - ONSEMI 控制器
页数 文件大小 规格书
24页 300K
描述
2/3/4-Phase Controller for CPU Applications

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中文翻译

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NCP5393AMNR2G 技术参数

是否无铅： 不含铅生命周期：Obsolete
零件包装代码：QFN包装说明：7 X 7 MM, 0.50 MM PITCH, LEAD FREE, QFN-48
针数：48Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.7
模拟集成电路 - 其他类型：SWITCHING CONTROLLER控制技术：PULSE WIDTH MODULATION
最大输入电压：5.25 V最小输入电压：4.75 V
标称输入电压：4.75 VJESD-30 代码：S-XQCC-N48
JESD-609代码：e3长度：7 mm
湿度敏感等级：1功能数量：1
端子数量：48最高工作温度：70 °C
最低工作温度：封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1 mm
表面贴装：YES切换器配置：BUCK
最大切换频率：1000 kHz温度等级：COMMERCIAL
端子面层：Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
Base Number Matches：1

NCP5393AMNR2G 数据手册

 浏览型号NCP5393AMNR2G的Datasheet PDF文件第2页浏览型号NCP5393AMNR2G的Datasheet PDF文件第3页浏览型号NCP5393AMNR2G的Datasheet PDF文件第4页浏览型号NCP5393AMNR2G的Datasheet PDF文件第5页浏览型号NCP5393AMNR2G的Datasheet PDF文件第6页浏览型号NCP5393AMNR2G的Datasheet PDF文件第7页 
NCP5393A  
Product Preview  
2/3/4-Phase Controller for  
CPU Applications  
The NCP5393A is a multiphase synchronous buck regulator  
controller designed to power the Core and Northbridge of an AMD  
microprocessor. The controller has a user configurable two, three, or  
four phase regulator for the Core and an independent single phase  
regulator to power the microprocessor Northbridge. The NCP5393A  
incorporates differential voltage sensing, differential phase current  
sensing, optional load−line voltage positioning, and programmable  
http://onsemi.com  
MARKING  
DIAGRAM  
V
DD  
and V  
offsets to provide accurately regulated power  
DDNB  
1
parallel− and serial−VID AMD processors. Dual−edge multiphase  
modulation provides the fastest initial response to dynamic load  
events. This reduces system cost by requiring less bulk and ceramic  
output capacitance to meet transient regulation specifications.  
High performance operational error amplifiers are provided to  
NCP5393A  
AWLYYWWG  
1
48  
QFN48, 7x7  
CASE 485AJ  
simplify compensation of the V and V  
regulators. Dynamic  
DD  
DDNB  
A
= Assembly Location  
= Wafer Lot  
Reference Injection further simplifies loop compensation by  
eliminating the need to compromise between response to load  
transients and response to VID code changes.  
Features  
WL  
YY  
WW  
G
= Year  
= Work Week  
= Pb−Free Package  
• Meets AMD’s Hybrid VR Specifications  
• Up to Four V Phases  
DD  
ORDERING INFORMATION  
• Single−Phase V  
Controller  
DDNB  
†
• Dual−Edge PWM for Fastest Initial Response to Transient Loading  
• High Performance Operational Error Amplifiers  
• Internal Soft Start and Slew Rate Limiting  
Device  
Package  
Shipping  
NCP5393AMNR2G QFN48  
2500 / Tape & Reel  
(Pb−Free)  
• Dynamic Reference Injection (Patent #US07057381)  
• DAC Range from 12.5 mV to 1.55 V  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specifications  
Brochure, BRD8011/D.  
• $0.5% DAC Accuracy fro 0.8 V to 1.55 V  
• V and V Offset Ranges 0 mV − 800 mV  
DD  
DD  
• True Differential Remote Voltage Sense Amplifiers  
• Phase−to−Phase I Current Balancing  
DD  
• Differential Current Sense Amplifiers for Each Phase of Each Output  
• “Lossless” Inductor Current Sensing for V and V  
Outputs  
Outputs  
DD  
DDNB  
• Supports Load Lines (Droop) for V and V  
DD  
DDNB  
• Oscillator Range of 100 kHz − 1 MHz  
• Tracking Over Voltage Protection  
• Output Inductor DCR−Based Over Current Protection for V and  
DD  
V
DDNB  
Outputs  
• Guaranteed Startup into Precharged Loads  
• Temperature Range: 0°C to 70°C  
• This is a Pb−Free Device  
Applications  
• Desktop Processors  
• Server Processors  
• High−End Notebook PCs  
This document contains information on a product under development. ON Semiconductor  
reserves the right to change or discontinue this product without notice.  
© Semiconductor Components Industries, LLC, 2008  
1
Publication Order Number:  
August, 2008 − Rev. P0  
NCP5393A/D  
1234567...24

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