NB7VPQ16M
1.8V/2.5V CML 12.5 Gbps
Programmable Pre-Emphasis
Copper/Cable Driver with
Selectable Equalizer Receiver
http://onsemi.com
Multi−Level Inputs w/ Internal Termination
MARKING
DIAGRAM*
Description
16
1
The NB7VPQ16M is a high performance single channel
programmable Pre−Emphasis CML Driver with a selectable Equalizer
Receiver that operates up to 14 Gbps typical with a 1.8 V or 2.5 V
power supply. When placed in series with a Data/Clock path, the
NB7VPQ16M inputs will compensate the degraded signal transmitted
across a FR4 PCB backplane or cable interconnect. Therefore, the
serial data rate is increased by reducing Inter−Symbol Interference
(ISI) caused by losses in copper interconnect or long cables.
The Pre−Emphasis buffer is controlled using a serial bus via the
Serial Data In (SDIN) and Serial Clock In (SCLKIN) control inputs
and contains circuitry which provides sixteen programmable
Pre−Emphasis settings to select the optimal output compensation
level.
NB7V
PQ16M
ALYWG
G
1
QFN−16
MN SUFFIX
CASE 485G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
These selectable output levels will handle various backplane lengths
and cable lines. The first four SDIN bits (D3:D0) will digitally select
0 dB through 12 dB typical of de−emphasis (see Table 1).
For cascaded applications, the shifted SDIN and SCLKIN signals
are presented at the SDOUT and SCLKOUT pins.
SDOUT
SDIN
SDI
SCLKIN
SLOAD
SCLKOUT
IN
IN
DAC
PE
VT
Q
Q
th
The 5 −bit (LSB) of the serial data bits allows for enabling the
equalization function of the receiver.
EQ
The differential Data / Clock inputs incorporate a pair of internal
50 W termination resistors, in a 100 W center−tapped configuration,
via the VT pin and will accept LVPECL, CML or LVDS logic levels.
This feature provides transmission line termination on−chip, at the
receiver end, eliminating external components.
The NB7VPQ16M is a member of the GigaComm™ Family of high
performance Data/Clock products with Pre−Emphasis/Equalization
(PEEQ).
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
Features
• Maximum Input Data Rate > 12.5 Gbps
• Maximum Input Clock Frequency > 8 GHz
• Drives Up To 18−inches of FR4
• (16) Programmable Output De−emphasis Levels; 0 dB
through 12 dB
• Operating Range: V = 1.71 V to 2.625 V, GND = 0 V
CC
• Internal Output Termination Resistors, 50 W
• QFN−16 Package, 3 mm x 3 mm
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
• 200 ps Typical Propagation Delay
• Differential CML Outputs, 400 mV Peak−to−Peak,
Typical (PE = 0 dB)
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
July, 2009 − Rev. 0
NB7VPQ16M/D