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NAND02GW4B2CZB1T PDF预览

NAND02GW4B2CZB1T

更新时间: 2024-11-06 19:13:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
57页 887K
描述
Flash, 128MX16, 35ns, PBGA63, 9.50 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, TFBGA-63

NAND02GW4B2CZB1T 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:BGA包装说明:9.50 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, TFBGA-63
针数:63Reach Compliance Code:compliant
ECCN代码:3A991.B.1.AHTS代码:8542.32.00.51
风险等级:5.24最长访问时间:35 ns
JESD-30 代码:R-PBGA-B63JESD-609代码:e0
长度:12 mm内存密度:2147483648 bit
内存集成电路类型:FLASH内存宽度:16
功能数量:1端子数量:63
字数:134217728 words字数代码:128000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128MX16
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
编程电压:3 V认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
类型:NAND TYPE宽度:9.5 mm
Base Number Matches:1

NAND02GW4B2CZB1T 数据手册

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NAND01G-B, NAND02G-B,  
NAND04G-B, NAND08G-B  
1 Gbit, 2 Gbit, 4 Gbit, 8 Gbit  
2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory  
PRELIMINARY DATA  
FEATURES SUMMARY  
HIGH DENSITY NAND FLASH MEMORIES  
Figure 1. Packages  
Up to 8 Gbit memory array  
Up to 64Mbit spare area  
Cost effective solutions for mass storage  
applications  
NAND INTERFACE  
TSOP48 12 x 20mm  
x8 or x16 bus width  
Multiplexed Address/ Data  
Pinout compatibility for all densities  
FBGA  
SUPPLY VOLTAGE  
1.8V device: V = 1.7 to 1.95V  
DD  
VFBGA63 9.5 x 12 x 1mm  
TFBGA63 9.5 x 12 x 1.2mm  
3.0V device: V = 2.7 to 3.6V  
DD  
PAGE SIZE  
x8 device: (2048 + 64 spare) Bytes  
x16 device: (1024 + 32 spare) Words  
DATA PROTECTION  
Hardware and Software Block Locking  
Hardware Program/Erase locked during  
Power transitions  
BLOCK SIZE  
x8 device: (128K + 4K spare) Bytes  
x16 device: (64K + 2K spare) Words  
DATA INTEGRITY  
PAGE READ / PROGRAM  
100,000 Program/Erase cycles  
10 years Data Retention  
RoHS COMPLIANCE  
Lead-Free Components are Compliant  
with the RoHS Directive  
DEVELOPMENT TOOLS  
Random access: 25µs (max)  
Sequential access: 50ns (min)  
Page program time: 300µs (typ)  
COPY BACK PROGRAM MODE  
Fast page copy without external buffering  
CACHE PROGRAM AND CACHE READ  
MODES  
Error Correction Code software and  
hardware models  
Bad Blocks Management and Wear  
Leveling algorithms  
PC Demo board with simulation software  
File System OS Native reference software  
Hardware simulation models  
Internal Cache Register to improve the  
program and read throughputs  
FAST BLOCK ERASE  
Block erase time: 2ms (typ)  
STATUS REGISTER  
ELECTRONIC SIGNATURE  
CHIP ENABLE ‘DON’T CARE’  
for simple interface with microcontroller  
SERIAL NUMBER OPTION  
October 2005  
1/57  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.  

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