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N16D1625LPAC2-75C PDF预览

N16D1625LPAC2-75C

更新时间: 2024-11-26 19:43:43
品牌 Logo 应用领域
美国芯成 - ISSI 时钟动态存储器内存集成电路
页数 文件大小 规格书
29页 214K
描述
Synchronous DRAM, 1MX16, 6ns, CMOS, PBGA60, GREEN, FBGA-60

N16D1625LPAC2-75C 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:VFBGA, BGA60,7X15,25Reach Compliance Code:compliant
风险等级:5.75访问模式:DUAL BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PBGA-B60
长度:10.1 mm内存密度:16777216 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:60字数:1048576 words
字数代码:1000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装等效代码:BGA60,7X15,25封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH电源:2.5 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.00001 A
子类别:DRAMs最大压摆率:0.045 mA
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:0.65 mm
端子位置:BOTTOM宽度:6.4 mm
Base Number Matches:1

N16D1625LPAC2-75C 数据手册

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N16D1625LPA  
512K x 16Bits x 2Banks Low Power Synchronous DRAM  
Description  
These N16D1625LPA are low power 16,777,216 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 16 bits. These  
products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are  
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input  
and output voltage levels are compatible with LVCMOS.  
Features  
ƒ JEDEC standard 2.5V power supply.  
• Auto refresh and self refresh.  
• All inputs and outputs referenced to the positive edge of the  
system clock.  
• All pins are compatible with LVCMOS interface.  
• 4K refresh cycle / 64ms.  
• Data mask function by DQM.  
• Internal dual banks operation.  
• Programmable Burst Length and Burst Type.  
- 1, 2, 4, 8 or Full Page for Sequential Burst.  
- 4 or 8 for Interleave Burst.  
• Burst Read Single Write operation.  
• Special Function Support.  
- PASR(Partial Array Self Refresh)  
• Programmable CAS Latency : 2,3 clocks.  
• Programmable Driver Strength Control  
- Full Strength or 1/2, 1/4 of Full Strength  
• Deep Power Down Mode.  
- Auto TCSR(Temperature Compensated Self Refresh)  
• Automatic precharge, includes CONCURRENT Auto Precharge  
Mode and controlled Precharge.  
Table1: Ordering Information  
Part No.  
Clock Freq.  
166 MHz  
133 MHz  
100 MHz  
166 MHz  
133 MHz  
100 MHz  
Temperature  
VDD/VDDQ  
Interface  
Package  
N16D1625LPAC2-60I  
N16D1625LPAC2-75I  
N16D1625LPAC2-10I  
N16D1625LPAT2-60I  
N16D1625LPAT2-75I  
N16D1625LPAT2-10I  
60-Ball Green  
FBGA  
-25°C to 85°C  
2.5V/2.5V  
LVCMOS  
50-Pin Green  
TSOPII  
1
Enable Semiconductor Corp. reserves the right to change products or specifications without notice.  
Ver. A  

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