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MX29F004BRC-12 PDF预览

MX29F004BRC-12

更新时间: 2024-11-03 21:05:55
品牌 Logo 应用领域
旺宏电子 - Macronix 光电二极管内存集成电路
页数 文件大小 规格书
33页 226K
描述
Flash, 512KX8, 120ns, PDSO32, 12 X 20 MM, PLASTIC, REVERSE, TSOP-32

MX29F004BRC-12 数据手册

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INDEX  
ADVANCED INFORMATION  
MX29F004T/B  
4M-BIT [512KX8] CMOS FLASH MEMORY  
FEATURES  
• 524,288 x 8 only  
• Erase suspend/Erase Resume  
- Suspends an erase operation to read data from,  
or program data to, another sector that is not being  
erased, then resumes the erase.  
• Status Reply  
- Data polling & Toggle bit for detection of program  
and erase cycle completion.  
• Chip protect/unprotect for 5V only system or 5V/  
12V system.  
• 100,000 minimum erase/program cycles  
• Latch-up protected to 100mA from -1V to VCC+1V  
• Low VCC write inhibit3.2V  
• Package type:  
- 32-pin PLCC, TSOP or PDIP  
• Single power supply operation  
- 5.0V only operation for read, erase and program  
operation  
• Fast access time: 70/90/120ns  
• Low power consumption  
- 30mA maximum active current  
- 1uA typical standby current  
• Command register architecture  
- Byte Programming (7us typical)  
- Block Erase  
(Block structure:16KB/8KB/8KB/32KB and 64KBx7)  
• Auto Erase (chip & block) and Auto Program  
- Automatically erase any combination of sectors  
with Erase Suspend capability.  
- Automatically program and verify data at specified  
address  
• Compatibility with JEDEC standard  
- Pinout and software compatible with single-power  
supply Flash  
GENERAL DESCRIPTION  
The MX29F004T/B is a 4-mega bit Flash memory  
organized as 512K bytes of 8 bits. MXIC's Flash  
memoriesofferthemostcost-effectiveandreliableread/  
write non-volatile random access memory. The  
MX29F004T/B is packaged in 32-pin PLCC, TSOP,  
PDIP. Itisdesignedtobereprogrammedanderasedin-  
system or in-standard EPROM programmers.  
during erase and programming, while maintaining  
maximum EPROM compatibility.  
MXIC Flash technology reliably stores memory  
contents even after 100,000 erase and program  
cycles. The MXIC cell is designed to optimize the  
erase and programming mechanisms. In addition,  
the combination of advanced tunnel oxide  
processing and low internal electric fields for erase  
and programming operations produces reliable  
cycling. The MX29F004T/B uses a 5.0V±10% VCC  
supply to perform the High Reliability Erase and  
auto Program/Erase algorithms.  
ThestandardMX29F004T/Boffersaccesstimesasfast  
as 70ns, allowing operation of high-speed  
microprocessors without wait states. To eliminate bus  
contention,theMX29F004T/Bhasseparatechipenable  
(CE) and output enable (OE ) controls.  
MXIC's Flash memories augment EPROM functionality  
with in-circuit electrical erasure and programming. The  
MX29F004T/Busesacommandregistertomanagethis  
functionality. The command register allows for 100%  
TTL level control inputs and fixed power supply levels  
The highest degree of latch-up protection is  
achieved with MXIC's proprietary non-epi process.  
Latch-up protection is proved for stresses up to  
100 milliamps on address and data pin from -1V to  
VCC + 1V.  
P/N:PM0554  
REV. 0.4, AUG. 01, 1998  
1

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