Datasheet > MX26L12811MC

MX26L12811MC

更新时间： 2024-11-22 05:51:39

品牌	Logo	应用领域
其他 - ETC		存储
页数	文件大小	规格书
32页	249K
描述
128M [x8/x16] SINGLE 3V PAGE MODE MTP MEMORY

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MX26L12811MC 数据手册

MX26L12811MC

128M[x8/x16] SINGLE3VPAGEMODEMTPMEMORY

FEATURES

• 3.0V to 3.6V operation voltage

• Block Structure

• High Performance

- Block erase time: 2s typ.

- 128 x 128Kbyte Erase Blocks

• Fast random / page mode access time

- Byte programming time: 210us typ.

- Block programming time: 0.8s typ. (using Write to

- 120/25 ns Read AccessTime (page depth:4-word)

• 32-Byte Write Buffer

Buffer Command)

• Program/Erase Endurance cycles: 10 cycles

- 6 us/byte Effective Programming Time

Packaging

Performance

- 44-Lead SOP

• Low power dissipation

- typical 15mA active current for page mode read

- 80uA/(max.) standby current

Technology

- Nbit (0.25u) MTPTechnology

GENERAL DESCRIPTION

The MXIC's MX26L12811MC series MTP use the most

advance 2 bits/cell Nbit technology, double the storage

capacity of memory cell. The device provide the high

density MTP memory solution with reliable performance

and most cost-effective.

command register to manage this functionality.

The MXIC's Nbit technology reliably stores memory con-

tents even after the specific erase and program cycles.

The MXIC cell is designed to optimize the erase and

program mechanisms by utilizing the dielectric's charac-

ter to trap or release charges from ONO layer.

The device organized as by 8 bits or by 16 bits of output

bus. The device is packaged in 44-Lead SOP. It is de-

signed to be reprogrammed and erased in system or in

standard EPROM programmers.

The device uses a 3.0V to 3.6V VCC supply to perform

the High Reliability Erase and auto Program/Erase algo-

rithms.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC + 1V.

The device offers fast access time and allowing opera-

tion of high-speed microprocessors without wait states.

The device augment EPROM functionality with in-circuit

electrical erasure and programming.The device uses a

P/N:PM0990

REV. 1.0, OCT. 29, 2003

12 3 4 5 6 7...32

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与MX26L12811MC相关器件

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MX26L12811MC-12	ETC	获取价格	128M [x8/x16] SINGLE 3V PAGE MODE MTP MEMORY
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