ADVANCED INFORMATION
MX26L3220
32M-BIT[2Mx16]CMOS
MULTIPLE-TIME-PROGRAMMABLEEPROM
FEATURES
• 2,097,152 x 16 byte structure
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program
operations
• Status Reply
- Data polling & Toggle bits provide detection of
programanderaseoperationcompletion
• 12V ACC input pin provides accelerated program
capability
• Low Vcc write inhibit is equal to or less than 2.5V
• Compatible with JEDEC standard
• HighPerformance
- Fast access time: 90/120ns (typ.)
- Fast program time: 70s/chip (typ.)
- Fast erase time: 90s/chip (typ.)
• LowPowerConsumption
• Output voltages and input voltages on the device is
deterined by the voltage on the VI/O pin.
- VI/O voltage range:1.65V~3.6V
• 10 years data retention
• Package
- 44-Pin SOP
- Low active read current: 17mA (typ.) at 5MHz
- Low standby current: 30uA (typ.)
• Minimum 100 erase/program cycle
- 48-Pin TSOP
- 48-Ball CSP
GENERAL DESCRIPTION
The MX26L3220 is a 32M bit MTP EPROMTM organized
as 2M bytes of 16 bits. MXIC's MTP EPROMTM offer the
most cost-effective and reliable read/write non-volatile
randomaccessmemory.TheMX26L3220ispackagedin
44-pinSOP,48-pinTSOPand48-ballCSP.Itisdesigned
tobereprogrammedanderasedinsystemorinstandard
EPROMprogrammers.
MXIC's MTP EPROMTM technology reliably stores
memory contents even after 100 erase and program
cycles. The MXIC cell is designed to optimize the erase
andprogrammechanisms.Inaddition,thecombinationof
advanced tunnel oxide processing and low internal
electric fields for erase and programming operations
produces reliable cycling.
The standard MX26L3220 offers access time as fast as
90ns,allowingoperationofhigh-speedmicroprocessors
without wait states. To eliminate bus contention, the
MX26L3220 has separate chip enable (CE) and output
enable OE controls. MXIC's MTP EPROMTM augment
EPROMfunctionalitywithin-circuitelectricalerasureand
programming.TheMX26L3220usesacommandregister
to manage this functionality.
The MX26L3220 uses a 2.7V to 3.6V VCC supply to
perform the High Reliability Erase and auto Program/
Erasealgorithms.
Thehighestdegreeoflatch-upprotectionisachievedwith
MXIC'sproprietarynon-epiprocess.Latch-upprotection
isprovedforstressesupto100milliampsonaddressand
data pin from -1V to VCC +1V.
P/N:PM0826
REV. 0.5, JAN. 29, 2002
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