MU9C3640L-90TZC

更新时间： 2024-01-29 22:51:51

品牌	Logo	应用领域
MUSIC		/
页数	文件大小	规格书
22页	185K
描述
LIST-XL Family

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数据手册

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MU9C3640L-90TZC 数据手册

Pin Descriptions

LIST-XL Family

PIN DESCRIPTIONS

All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW.

Inputs should never be left floating. The CAM architecture draws large currents during compare operations, mandating the

use of good layout and bypassing techniques. Refer to the Electrical Characteristics section for more information.

/E (Chip Enable, Input, TTL)

/FF (Full Flag, Output, TTL)

The/EinputenablesthedevicewhileLOW. Thefallingedge

registersthecontrolsignals/Wand/CM.Therisingedgeturns

off the DQ pins and clocks the Destination and Source

Segment counters. The four cycle types enabled by /E are

shown in Table 2 on page 2.

The/FFoutputgoesLOWwhennoemptymemorylocations

exist within the device.

/RESET (Reset, Input, TTL)

/RESET must be driven LOW to place the device in aknown

state before operation, which will reset the device to the

conditionsshowninTable4onpage8.The/RESETpinshould

be driven by TTL levels, not directly by an RC time-out. /E

must be kept HIGH during /RESET.

/W (Write Enable, Input, TTL)

The/Winputselectsthedirectionofdataflowduringadevice

cycle. /W LOW selects a Write cycle and /W HIGH selects

a Read cycle.

VCC, GND (positive Power Supply, Ground)

ThesepinsarethepowersupplyconnectionstotheLISTXL.

VCC must meet the voltage supply requirements in the

OperatingConditionssectionrelativetotheGNDpins,which

are at 0 Volts (system reference potential), for correct

operation of the device. All the ground and power pins must

beconnectedtotheirrespectiveplaneswithadequatebulkand

highfrequencybypassingcapacitorsincloseproximitytothe

device.

/CM (DATA/Command Select, Input, TTL)

The /CM input selects whether the input signals on DQ15-0

are data or commands. /CM LOW selects Command cycles

and /CM HIGH selects Data cycles.

/DQ15-0 (Data Bus, I/O, TTL)

The DQ15-0 lines convey data, commands, and status to and

from the LIST-XL. /W and /CM controls the direction and

nature of the information that flows to or from the

device.When /E is HIGH, DQ15-0 go to Hi-Z.

/MF (Match Flag, Output, TTL)

The /MF output goes LOW when one or more valid matches

occur during the current or most recent compare cycle. /MF

isHIGHifthereisnomatch./MFwillberesetwhentheactive

configuration register set is changed.

/MM (Device Multiple Match Flag, Output, TTL)

The /MM output is LOW when more than one valid match

occurs during the current or the most recent compare cycle.

/MM will be reset when the active register set is changed.

Rev. 3.1

1 234 5 6 7...22

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与MU9C3640L-90TZC相关器件

型号	品牌	获取价格	描述	数据表
MU9C3640L-90TZI	MUSIC	获取价格	LIST-XL Family
MU9C3640LF-70TZC	MUSIC	获取价格	Content Addressable SRAM, 256X64, 70ns, CMOS, PQFP32
MU9C3640LF-90TZC	MUSIC	获取价格	Content Addressable SRAM, 256X64, 90ns, CMOS, PQFP32
MU9C4160-11DC	MUSIC	获取价格	Palette DAC, 1280 X 1024 Pixels, CMOS, PQCC44
MU9C4160-11QAC	MUSIC	获取价格	Palette DAC, 1280 X 1024 Pixels, CMOS, PQFP44
MU9C4160-12DC	MUSIC	获取价格	Palette DAC, 1280 X 1024 Pixels, CMOS, PQCC44
MU9C4160-12QAC	MUSIC	获取价格	Palette DAC, 1280 X 1024 Pixels, CMOS, PQFP44
MU9C4160-14DC	MUSIC	获取价格	Palette DAC, 1280 X 1024 Pixels, CMOS, PQCC44
MU9C4160-14QAC	MUSIC	获取价格	Palette DAC, 1280 X 1024 Pixels, CMOS, PQFP44
MU9C4160-90DC	MUSIC	获取价格	Palette DAC, 1280 X 1024 Pixels, CMOS, PQCC44

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