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MT9161BE PDF预览

MT9161BE

更新时间: 2024-01-27 01:24:00
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 解码器编解码器电信集成电路电信电路光电二极管PC
页数 文件大小 规格书
30页 423K
描述
5 Volt Multi-Featured Codec (MFC)

MT9161BE 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP24,.4Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.85
其他特性:HALF DUPLEX压伸定律:A/MU-LAW
滤波器:YES最大增益公差:0.2 dB
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
长度:15.4 mm线性编码:NOT AVAILABLE
湿度敏感等级:1功能数量:1
端子数量:24工作模式:SYNCHRONOUS/ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP24,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:5 V认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Codecs
标称供电电压:5 V表面贴装:YES
技术:CMOS电信集成电路类型:PROGRAMMABLE CODEC
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmBase Number Matches:1

MT9161BE 数据手册

 浏览型号MT9161BE的Datasheet PDF文件第3页浏览型号MT9161BE的Datasheet PDF文件第4页浏览型号MT9161BE的Datasheet PDF文件第5页浏览型号MT9161BE的Datasheet PDF文件第7页浏览型号MT9161BE的Datasheet PDF文件第8页浏览型号MT9161BE的Datasheet PDF文件第9页 
MT9160B/61B  
Advance Information  
Motorola/National operation. Refer to the relative  
timing diagrams of Figures 5 and 6.  
Flexible Digital Interface  
A serial link is required to transport data between the  
MT9160B/61B and an external digital transmission  
device. The MT9160B/61B utilizes the ST-BUS  
architecture defined by Zarlink Semiconductor but  
Receive data is sampled on the rising edge of SCLK  
while transmit data is made available concurrent with  
the falling edge of SCLK.  
COMMAND/ADDRESS  
DATA INPUT/OUTPUT  
COMMAND/ADDRESS:  
DATA 1  
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
RECEIVE  
D
D
D
D
D
D
D
DATA 1  
TRANSMIT  
0
1
2
3
4
5
6
7
0
1
2
3
4
5 6  
7
SCLK  
CS  
Delays due to internal processor timing which are transparent.  
The MT9160:-latches received data on the rising edge of SCLK.  
-outputs transmit data on the falling edge of SCLK.  
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The  
subsequent byte is always data until terminated via CS returning high.  
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.  
D
D
0
7
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write  
3 bits - Addressing Data  
4 bits - Unused  
X
X
X
X
A
A
A
0
R/W  
2
1
Figure 4 - Serial Port Relative Timing for Intel Mode 0  
COMMAND/ADDRESS:  
COMMAND/ADDRESS  
DATA INPUT/OUTPUT  
DATA 2  
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RECEIVE  
D
D
D
D
D
D
D
DATA 1  
TRANSMIT  
7
6
5
4
3
2
1
0
7
6
5
4
3
2 1  
0
SCLK  
CS  
Delays due to internal processor timing which are transparent.  
The MT9160:-latches received data on the rising edge of SCLK.  
-outputs transmit data on the falling edge of SCLK.  
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The  
subsequent byte is always data until terminated via CS returning high.  
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.  
D
D
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write  
3 bits - Addressing Data  
4 bits - Unused  
7
0
A
R/W  
X
X
X
A
A
X
2
1
0
Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire  
84  

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