MT9161BE

更新时间： 2024-01-06 19:07:11

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		解码器编解码器电信集成电路电信电路光电二极管 PC
页数	文件大小	规格书
30页	423K
描述
5 Volt Multi-Featured Codec (MFC)

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技术参数
数据手册

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MT9161BE 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SOP, SOP24,.4	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.85
其他特性：	HALF DUPLEX	压伸定律：	A/MU-LAW
滤波器：	YES	最大增益公差：	0.2 dB
JESD-30 代码：	R-PDSO-G24	JESD-609代码：	e0
长度：	15.4 mm	线性编码：	NOT AVAILABLE
湿度敏感等级：	1	功能数量：	1
端子数量：	24	工作模式：	SYNCHRONOUS/ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP24,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	240
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	2.65 mm	子类别：	Codecs
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	PROGRAMMABLE CODEC
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	7.5 mm	Base Number Matches：	1

MT9161BE 数据手册

Advance Information

MT9160B/61B

Filter/Codec and Transducer Interface

Serial

Port

Default Bypass

HSPKR +

-8.05 dB or

-2.05 dB

Receive

Filter Gain

0 to -7 dB

(1 dB steps)

Handset

Receiver

(150Ω)

Decoder

2.05dB

PCM

Receiver

Driver

75Ω

HSPKR -

-6 dB

75Ω

Side-tone

-9.96 to

+9. 96 dB

(3.32 dB steps)

-11 dB

M+

M-

Transmit

Transmit Filter

PCM

Transmit Filter

Transmitter

Microphone

Transmit Gain

Encoder

-2.05dB

Gain

-0.37 dB or 8.93 dB

0 to +7 dB

(1 dB steps)

8.42 dB

out

(1 dB steps)

INTERNAL TO DEVICE

EXTERNAL TO DEVICE

Figure 3 - Audio Gain Partitioning

(DATA2), a chip select pin (CS) and a synchronous

data clock pin (SCLK). For D-channel contention

control, in ST-BUS mode, this interface provides an

open-drain interrupt output (IRQ).

All data transfers through the microport are two-byte

transfers requiring the transmission of a Command/

Address byte followed by the data byte written or

read from the addressed register. CS must remain

asserted for the duration of this two-byte transfer. As

shown in Figures 5 and 6 the falling edge of CS

indicates to the MT9160B/61B that a microport

transfer is about to begin. The ﬁrst 8 clock cycles of

SCLK after the falling edge of CS are always used to

receive the Command/Address byte from the

The microport dynamically senses the state of the

serial clock (SCLK) each time chip select becomes

active. The device then automatically adjusts its

internal timing and pin conﬁguration to conform to

Intel or Motorola/National requirements. If SCLK is

high during chip select activation then Intel mode 0

timing is assumed. The DATA1 pin is deﬁned as a

bi-directional (transmit/receive) serial port and

DATA2 is internally disconnected. If SCLK is low

during chip select activation then Motorola/National

timing is assumed. Motorola processor mode

CPOL=0, CPHA=0 must be used. DATA1 is deﬁned

as the data transmit pin while DATA2 becomes the

data receive pin. Although the dual port Motorola

controller conﬁguration usually supports full-duplex

communication, only half-duplex communication is

possible in the MT9160B/61B. The micro must

discard non-valid data which it clocks in during a

valid write transfer to the MT9160B/61B. During a

valid read transfer from the MT9160B/61B data

simultaneously clocked out by the micro is ignored

by the MT9160B/61B.

microcontroller. The

Command/Address

byte

contains information detailing whether the second

byte transfer will be a read or a write operation and

at what address. The next 8 clock cycles are used to

transfer the data byte between the MT9160B/61B

and the microcontroller. At the end of the two-byte

transfer CS is brought high again to terminate the

session. The rising edge of CS will tri-state the

output driver of DATA1 which will remain tri-stated as

long as CS is high.

Intel processors utilize least signiﬁcant bit ﬁrst

transmission while Motorola/National processors

employ most signiﬁcant bit ﬁrst transmission. The

MT9160B/61B

microport

automatically

accommodates these two schemes for normal data

bytes. However, to ensure decoding of the R/W and

address information, the Command/Address byte is

deﬁned differently for Intel operation than it is for

1 2 3 456 7 8...30

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与MT9161BE相关器件

型号	品牌	描述	获取价格	数据表
MT9161BN	MITEL	ISO2-CMOS 5 Volt Multi-Featured Codec (MFC)	获取价格
MT9161BN	ZARLINK	5 Volt Multi-Featured Codec (MFC)	获取价格
MT9161BS	ZARLINK	5 Volt Multi-Featured Codec (MFC)	获取价格
MT9161BS	MITEL	ISO2-CMOS 5 Volt Multi-Featured Codec (MFC)	获取价格
MT9162	MITEL	ISO2-CMOS 5 Volt Single Rail Codec	获取价格
MT9162	ZARLINK	5 Volt Single Rail Codec	获取价格

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