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MT9171 PDF预览

MT9171

更新时间: 2024-11-30 22:49:59
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
25页 403K
描述
ISO2-CMOS ST-BUS FAMILY

MT9171 数据手册

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ISO2-CMOS ST-BUS FAMILY MT9171/72  
Digital Subscriber Interface Circuit  
Digital Network Interface Circuit  
DS5130  
ISSUE 3  
February 1999  
Features  
Ordering Information  
Full duplex transmission over a single twisted  
pair  
MT9171AE  
MT9171AN  
MT9171AP  
MT9172AE  
MT9172AN  
MT9172AP  
22 Pin Plastic DIP (400 mil)  
24 Pin SSOP  
28 Pin PLCC  
22 Pin Plastic DIP (400 mil)  
24 Pin SSOP  
28 Pin PLCC  
Selectable 80 or 160 kbit/s line rate  
Adaptive echo cancellation  
Up to 3km (9171) and 4 km (9172)  
ISDN compatible (2B+D) data format  
Transparent modem capability  
Frame synchronization and clock extraction  
Zarlink ST-BUS compatible  
-40°C to +85°C  
Description  
The MT9171 (DSIC) and MT9172 (DNIC) are pin for  
pin compatible replacements for the MT8971 and  
MT8972, respectively. They are multi-function  
devices capable of providing high speed, full duplex  
digital transmission up to 160 kbit/s over a twisted  
Low power (typically 50 mW), single 5V supply  
Applications  
wire pair.  
They use adaptive echo-cancelling  
techniques and transfer data in (2B+D) format  
compatible to the ISDN basic rate. Several modes of  
operation allow an easy interface to digital  
telecommunication networks including use as a high  
speed limited distance modem with data rates up to  
160 kbit/s. Both devices function identically but with  
the DSIC having a shorter maximum loop reach  
specification. The generic "DNIC" will be used to  
reference both devices unless otherwise noted.  
Digital subscriber lines  
High speed data transmission over twisted  
wires  
Digital PABX line cards and telephone sets  
80 or 160 kbit/s single chip modem  
2
The MT9171/72 is fabricated in Zarlink’s ISO -  
CMOS process.  
DSTi/Di  
L
Differentially  
Encoded Biphase  
Transmitter  
Transmit  
Filter &  
Line Driver  
OUT  
Transmit  
Interface  
Prescrambler  
Scrambler  
CDSTi/  
CDi  
L
OUT  
DIS  
V
Bias  
Control  
Transmit  
Address  
Echo Canceller  
Error  
Signal  
Register  
Timing  
F0/CLD  
MUX  
Master Clock  
Phase Locked  
Precan  
C4/TCK  
F0o/RCK  
MS0  
Echo Estimate  
Transmit/  
Clock  
Receive  
Timing &  
Control  
+
-1  
Receive  
Filter  
DPLL  
MS1  
+2  
L
IN  
MS2  
Sync Detect  
Receive  
RegC  
Status  
OSC2  
OSC1  
DSTo/Do  
Differentially  
Encoded Biphase  
Receiver  
De-  
Prescrambler  
Receive  
Interface  
Descrambler  
CDSTo/  
CDo  
V
V
V
V
DD  
SS  
Bias Ref  
Figure 1 - Functional Block Diagram  
9-115  

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