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MT89L86 PDF预览

MT89L86

更新时间: 2024-01-16 20:00:34
品牌 Logo 应用领域
MITEL 开关
页数 文件大小 规格书
40页 175K
描述
CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch

MT89L86 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.27
JESD-30 代码:S-PQCC-J44JESD-609代码:e0
长度:16.585 mm湿度敏感等级:1
功能数量:1端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:4.57 mm标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:DIGITAL TIME SWITCH温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:16.585 mm
Base Number Matches:1

MT89L86 数据手册

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MT89L86  
Advance Information  
Pin Description (continued)  
Pin #  
Name  
Description  
44  
48  
PLCC SSOP  
36 39  
STo6/A6 ST-BUS Output 6/Address 6 input (Three-state output/input). The function of this  
pin is determined by the switching configuration enabled. If non-multiplexed CPU bus is  
used along with a higher data rate employing 8.192 or 4.096 Mb/s, this pin provides the  
A6 address input function. For 2.048 Mb/s applications or when the multiplexed CPU  
bus interface is selected, this pin assumes STo6 function. See Tables 1, 2, 6 & 7 for  
more details.  
Note that for applications where both A6 input and STo6 output are required  
simultaneously (e.g., 4.096 to 2.048 Mb/s or 8.192 to 2.048 Mb/s rate conversion  
applications), the A6 input should be connected to pin STi6/A6.  
37-39 40-42 STo5-0 ST-BUS Outputs 5 to 0 (Three-state Outputs). Serial data output streams. These  
41-43 44-46  
serial streams may be composed of 32, 64 and 128 channels at data rates of 2.048,  
4.096 or 8.192 Mbit/s, respectively.  
44  
47  
ODE  
Output Drive Enable (5V-tolerant Input). This is the output enable input for the STo0  
to STo9 serial outputs. If this input is low STo0-9 are high impedance. If this input is  
high each channel may still be set to high impedance by using per-channel control bits  
in Connect Memory High.  
1
6
48  
6
CSTo  
Control ST-BUS Output (Output). This is a 2.048 Mb/s output containing 256 bits per  
frame. The level of each bit is determined by the CSTo bit in the Connect Memory high  
locations.  
AS/ALE Address Strobe or Latch Enable (5V-tolerant Input). This input is only used if  
multiplexed bus is selected via the IM input pin.  
The falling edge of this signal is used to sample the address into the address latch  
circuit. When the non-multiplexed bus interface is selected, this input is not required  
and should be connected to ground.  
18  
28  
19  
30  
IM  
CPU Interface Mode (5V-tolerant Input). If HIGH, this input configures the MT89L86  
in the multiplexed microprocessor bus mode. When this input pin is connected to  
ground, the MT89L86 assumes non-multiplexed CPU interface.  
STi15/ ST-BUS Input 15 / ST-BUS Output 9 (Input/three-state output). This pin is only used  
STo9  
if multiplexed CPU bus is selected. If 16-input x 8-output switching configuration is  
enabled in the SCB bits (IMS register), this pin is an input receiving serial ST-BUS  
stream 15 at a data rate of 2.048 Mbit/s.  
If Stream Pair Selection capability is enabled (see switching configuration section), this  
pin is the ST-BUS stream 9 output.  
When non-multiplexed bus structure is used, this pin should be connected to ground.  
40  
43  
STi14/ ST-BUS Input 14 / ST-BUS Output 8 (Input/three-state output). This pin is only used  
STo8  
if multiplexed CPU bus is selected. If 16-input x 8-output switching configuration is  
enabled in the SCB bits (IMS register), this pin is an input that receives serial ST-BUS  
stream 14 at a data rate of 2.048 Mbit/s.  
If Stream Pair Selection capability is enabled (see switching configuration section), this  
pin is the ST-BUS stream 8 output.  
When non-multiplexed bus structure is used, this pin should be connected to ground.  
4

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