CMOS ST-BUS FAMILY
MT89L85
Enhanced Digital Switch
Advance Information
DS5194
ISSUE 2
September 1999
Features
Ordering Information
MT89L85AP 44 Pin PLCC
MT89L85AN 48 Pin SSOP
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3.3 volt supply
5V tolerant inputs and TTL compatible outputs
256 x 256 channel non-blocking switch
-40°C to +85°C
Programmable frame integrity for wideband
channels
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Automatic identification of ST-BUS/GCI
interface backplanes
Description
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Per channel tristate control
The MT89L85 Enhanced Digital Switch device is an
upgraded 3-volt version of the MT8985 Digital
Switch. It is pin compatible with the MT8985 and
retains all of the MT8985's functionality. The
enhanced digital swtich is designed for switching
PCM-encoded voice or data, under microprocessor
control, in digital exchanges, PBXs and any ST-BUS/
MVIP environment. It provides simultaneous
connections for up to 256 64kb/s channels. Each of
the eight serial inputs and outputs consist of 32 64
kbit/s channels multiplexed to form a 2048 kbit/s
stream. As the main function in switching
applications, the device provides per-channel
selection between variable or constant throughput
delays. The constant throughput delay feature allows
grouped channels such as ISDN H0 to be switched
through the device maintaining its sequence
integrity. The MT89L85 is ideal for medium sized
mixed voice/data switch and voice processing
applications.
Patented message mode
Non-multiplexed microprocessor interface
Available in PLCC-44 and SSOP-48 packages
Pin compatible with MT8985 device
Low power consumption
Applications
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Medium size digital switch matrices
Hyperchannel switching (e.g., ISDN H0)
™
ST-BUS/MVIP
interface functions
Serial bus control and monitoring
Centralized voice processing systems
Data multiplexer
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ODE
V
V
F0i RESET
C4i
SS
DD
Frame
Counter
Output
MUX
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
Parallel
to
Serial
to
Data
Memory
Serial
Parallel
Converter
Control Register
Control Interface
Converter
Connection
Memory
DS CS R/W A5/ DTA D7/
A0 D0
CSTo
** for 48-pin SSOP only
Figure 1 - Functional Block Diagram
1