Datasheet > MT89L85AN

MT89L85AN

更新时间： 2024-01-29 00:56:48

品牌	Logo	应用领域
MITEL		开关
页数	文件大小	规格书
20页	136K
描述
CMOS ST-BUS⑩ FAMILY Enhanced Digital Switch

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中文翻译

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技术参数
数据手册

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MT89L85AN 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	LPCC
针数：	44	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.88
JESD-30 代码：	S-PQCC-J44	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC44,.7SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Other Telecom ICs
最大压摆率：	7 mA	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD

MT89L85AN 数据手册

Advance Information

MT89L85

Variable Delay mode

To summarize, any input time slot from input frame N

will be always switched to the destination time slot on

output frame N+2. In Constant Delay mode, the

device throughput delay is calculated according to

the following formula:

The delay in this mode is dependent only on the

combination of source and destination channels and

it is not dependent on the input and output streams.

The minimum delay achievable in the MT89L85

device is 3 time slots. In the MT89L85 device, the

information that is to be output in the same channel

position as the information is input (position n),

relative to frame pulse, will be output in the following

frame (channel n, frame n+1). The same occurs if

the input channel has to be output in the two

channels succeeding (n+1 and n+2) the channel

position as the information is input.

DELAY = [32 + (32 - IN) + (OUT - 1)];

(expressed in number of time slots)

Where:

IN is the number of the input time slot

(from 1 to 32).

OUT is the number of the output time slot

(from 1 to 32).

The information switched to the third timeslot after

the input has entered the device (for instance, input

channel 0 to output channel 3 or input channel 30 to

output channel 1), is always output three channels

later.

Microprocessor Port

The MT89L85 microprocessor port has pin

compatibility with Mitel MT8985 Digital Switch

devices providing a non-multiplexed bus architecture.

The parallel port consists of an 8 bit parallel data bus

(D0-D7), six address input lines (A0-A5) and four

control lines (CS, DS, R/W and DTA). This parallel

microport allows the access to the Control registers,

Connection Memory High, Connection Memory Low

and the Data Memory. All locations are read/written

except for the data memory which can be read only.

Any switching conﬁguration that provides three or

more timeslots between input and output channels,

will have a throughput delay equal to the difference

between the output and input channels; i.e., the

throughput delay will be less than one frame. Table 1

shows the possible delays for the MT89L85 device in

Variable Delay mode:

Accesses from the microport to the connection

memory and the data memory are multiplexed with

accesses from the input and output TDM ports. This

can cause variable Data Acknowledge delays (DTA).

Input

Channel

Output

Channel

Throughput Delay

m=n, n+1 or

n+2

m-n + 32 timeslots

A5 A4 A3 A2 A1 A0

LOCATION

m>n+2

m<n

m-n time slots

•

ControlRegister

32-(n-m) time slots

Channel 0

Channel 1

Table 1 - Channel Delay for the Variable Delay

Mode

•

Constant Delay Mode

•

In this mode frame integrity is maintained in all

switching conﬁgurations by making use of a multiple

Data-Memory buffer technique where input channels

written in any of the buffers during frame N will be

read out during frame N+2. In the MT89L85, the

minimum throughput delay achieve-able in Constant

Delay mode will be 32 time slots; for example, when

input time slot 32 (channel 31) is switched to output

time slot 1 (channel 0). Likewise, the maximum delay

is achieved when the ﬁrst time slot in a frame

(channel 0) is switched to the last time slot in the

frame (channel 31), resulting in 94 time slots of

delay.

Channel 31

Figure 3 - Address Memory Map

Note: "x" Don’t care

Software Control

The address lines on the microprocessor interface

give access to the MT89L85 internal registers and

memories. If the A5,A1,A0 address line inputs are

LOW, then the MT89L85 Internal Control Register is

addressed (see Figure 3). If A5 input line is HIGH,

then the remaining address input lines are used to

select Memory subsections of 32 locations

corresponding to the number of channels per input or

output stream. As explained in the Control register

2-5

1 2 3 456 7 8...20

中文翻译

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与MT89L85AN相关器件

型号	品牌	获取价格	描述	数据表
MT89L85ANR	MICROSEMI	获取价格	Telecom IC, CMOS, PDSO48
MT89L85ANR1	ZARLINK	获取价格	Digital Time Switch, CMOS, PDSO48, 0.300 INCH, LEAD FREE, PLASTIC, MO-118AA, SSOP-48
MT89L85AP	MITEL	获取价格	CMOS ST-BUS⑩ FAMILY Enhanced Digital Switch
MT89L85AP1	ZARLINK	获取价格	Digital Time Switch, CMOS, PQCC44, LEAD FREE, PLASTIC, MS-018AC, LCC-44
MT89L85AP1	MICROSEMI	获取价格	Digital Time Switch, CMOS, PQCC44, LEAD FREE, PLASTIC, MS-018AC, LCC-44
MT89L85APR	MICROSEMI	获取价格	Telecom IC, CMOS, PQCC44
MT89L85APR1	MICROSEMI	获取价格	Digital Time Switch, PQCC44, LEAD FREE, PLASTIC, MS-018AC, LCC-44
MT89L86	MITEL	获取价格	CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Swi
MT89L86AN	MITEL	获取价格	CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Swi
MT89L86AN	MICROSEMI	获取价格	Digital Time Switch, CMOS, PDSO48, SSOP-48

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