5秒后页面跳转
捷配首页

Datasheet > MT8931CE
MT8931CE PDF预览

MT8931CE

更新时间： 2024-01-08 17:41:30
品牌 Logo 应用领域
MITEL 网络接口电信集成电路光电二极管综合业务数字网
页数 文件大小 规格书
40页 311K
描述
CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit Preliminary Information

阅读下载

获取价格

MT8931CE 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：LPCC
包装说明：QCCJ,针数：44
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.76JESD-30 代码：S-PQCC-J44
JESD-609代码：e0长度：16.585 mm
湿度敏感等级：1功能数量：1
端子数量：44最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：225
认证状态：Not Qualified座面最大高度：4.57 mm
标称供电电压：5 V表面贴装：YES
技术：CMOS电信集成电路类型：DIGITAL SLIC
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：16.585 mmBase Number Matches：1

MT8931CE 数据手册

 浏览型号MT8931CE的Datasheet PDF文件第1页浏览型号MT8931CE的Datasheet PDF文件第2页浏览型号MT8931CE的Datasheet PDF文件第4页浏览型号MT8931CE的Datasheet PDF文件第5页浏览型号MT8931CE的Datasheet PDF文件第6页浏览型号MT8931CE的Datasheet PDF文件第7页 
MT8931C  
Pin Description (continued)  
Pin #  
Name  
Description  
DIP PLCC  
9
16  
17  
R/W/WR Read/Write or Write Input: defines the data bus transfer as a read (R/W=1) or a write  
(R/W=0) in Motorola bus mode. Redefined to WR in Intel bus mode.  
10  
DS/RD Data Strobe/Read Input: active high input indicates to the SNIC that valid data is on  
the bus during a write operation or that the SNIC must output data during a read  
operation in Motorola bus mode. Redefined to RD in Intel bus mode.  
11  
19  
AS/ALE Address Strobe/Address Latch Enable Input: in Motorola bus mode the falling edge  
is used to strobe the address into the SNIC during microprocessor access. Redefined  
to ALE in Intel bus mode.  
12  
13  
20  
21  
CS  
Chip Select Input: active low, used to select the SNIC for microprocessor access.  
IRQ  
Interrupt Request (Open Drain Output): an output indicating an unmasked HDLC  
interrupt. The interrupt remains active until the microprocessor clears it by reading the  
HDLC Interrupt Status Register. This interrupt source is enabled with B2=0 of Master  
Control Register.  
New Data Available (Open Drain Output): an active low output signal indicating  
availability of new data from the S-Bus. This signal is selected with B2=1 of Master  
Control Register. This pin must be tied to VDD with a 10kΩ resistor.  
NDA  
14  
22  
VSS  
Ground.  
15- 24-26,  
22 30-32,  
34-35  
AD0-7  
Bidirectional Address/Data Bus: electrically and logically compatible to either Intel or  
Motorola micro-bus specifications. If DS/RD is low on the rising edge of AS/ALE then  
the chip operates to Motorola specs. If DS/RD is high on the rising edge of AS/ALE Intel  
mode is selected. Taking Rsti low sets Motorola mode.  
23  
24  
37  
38  
Rsti  
Reset Input: Schmitt trigger reset input. If ’0’, sets all control registers to the default  
conditions, resets activation state machines to the deactivated state, resets HDLC,  
clears the HDLC FIFO‘s. Sets the microport to Motorola bus mode.  
STAR/Rsto Star/Reset (Open Drain Output): 192kbit/s Rx data output fixed relative to the ST-  
BUS timebase. A group of NTs, in fixed timing mode, can be wire or’ed together to  
create a Star configuration. Active low reset output in TE mode indicating 128  
consecutive marks have been received. Can be connected directly to Rsti to allow NT  
to reset all TEs on the bus. This pin must be tied to VDD with a 10 kΩ resistor.  
25  
40  
LRx  
Receive Line Signal Input: this is a high impedance input for the pseudoternary line  
signal to be connected to the line through a 2:1 ratio transformer. See Figures 20 and  
21. A DC bias level on this input equal to V  
must be maintained.  
Bias  
26  
27  
28  
42  
43  
44  
LTx  
Transmit Line Signal Output: this is a current source output designed to drive a  
nominal 50 ohm line through a 2:1 ratio transformer. See Figures 20 and 21.  
VBias  
Bias Voltage: analog ground for Tx and Rx transformers. This pin must be decoupled  
to VDD through a 10µF capacitor with good high frequency characteristics.  
VDD  
NC  
Power Supply Input.  
No Connection.  
1,5-6,10-  
12,15,18,  
23,27-  
29, 33,  
36, 39,  
41  
9-73  
1234567...40

下载PDF

与MT8931CE相关器件

型号 品牌 描述 获取价格 数据表
MT8931CP ZARLINK Subscriber Network Interface Circuit

获取价格
MT8931CP MITEL CMOS ST-BUS⑩ FAMILY Subscriber Network Interf

获取价格
MT8931CPR ZARLINK Digital SLIC, 1-Func, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44

获取价格
MT8940 MITEL ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk

获取价格
MT8940-1 MITEL ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk

获取价格
MT8940AC MITEL T1/CEPT Digital Trunk PLL

获取价格

与MT8931CE相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证