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MT8941BE PDF预览

MT8941BE

更新时间: 2024-01-26 22:05:31
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信集成电路电信电路光电二极管
页数 文件大小 规格书
27页 493K
描述
Advanced T1/CEPT Digital Trunk PLL

MT8941BE 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.88
Is Samacsys:NJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.505 mm
湿度敏感等级:1功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Other Telecom ICs最大压摆率:0.015 mA
标称供电电压:5 V表面贴装:YES
技术:CMOS电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:11.505 mmBase Number Matches:1

MT8941BE 数据手册

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MT8941B  
Advanced T1/CEPT Digital Trunk PLL  
Data Sheet  
February 2005  
Features  
Provides T1 clock at 1.544 MHz locked to an 8  
Ordering Information  
kHz reference clock (frame pulse)  
MT8941BE  
24 Pin PDIP  
Tubes  
MT8941BP  
28 Pin PLCC  
Tubes  
Provides CEPT clock at 2.048 MHz and ST-BUS  
clock and timing signals locked to an internal or  
external 8 kHz reference clock  
MT8941BPR 28 Pin PLCC  
Tape & Reel  
MT8941BP1 28 Pin PLCC* Tubes  
MT8941BPR1 28 Pin PLCC* Tape & Reel  
Typical inherent output jitter (unfiltered)= 0.07 UI  
peak-to-peak  
*Pb Free Matte Tin  
-40°C to +85°C  
Typical jitter attenuation at: 10 Hz=23 dB,100  
Description  
Hz=43 dB, 5 to 40 kHz 64 dB  
Jitter-free “FREE-RUN” mode  
Uncommitted two-input NAND gate  
Low power CMOS technology  
The MT8941B is a dual digital phase-locked loop  
providing the timing and synchronization signals for the  
T1 or CEPT transmission links and the ST-BUS. The  
first PLL provides the T1 clock (1.544 MHz)  
synchronized to the input frame pulse at 8 kHz. The  
timing signals for the CEPT transmission link and the  
ST-BUS are provided by the second PLL locked to an  
internal or an external 8 kHz frame pulse signal.  
Applications  
Synchronization and timing control for T1  
and CEPT digital trunk transmission links  
ST- BUS clock and frame pulse source  
The MT8941B offers improved jitter performance over  
the MT8940. The two devices also have some  
functional differences, which are listed in the section on  
“Differences between MT8941B and MT8940”.  
CVb  
F0i  
Variable  
DPLL #1  
CV  
Clock  
Control  
2:1 MUX  
C12i  
ENCV  
MS0  
Frame Pulse  
Control  
Mode  
Selection  
Logic  
MS1  
MS2  
F0b  
Input  
Selector  
MS3  
C8Kb  
C4b  
4.096 MHz  
Clock  
C4o  
Control  
ENC4o  
C16i  
DPLL #2  
C2o  
Clock  
2.048 MHz  
Clock  
Generator  
C2o  
Control  
Ai  
Bi  
ENC2o  
Yo  
VDD  
VSS  
RST  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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