Datasheet > MT8941AE

MT8941AE

更新时间： 2024-02-20 22:22:08

品牌	Logo	应用领域
MITEL		/
页数	文件大小	规格书
18页	249K
描述
CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL

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数据手册

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MT8941AE 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QCCJ, LDCC28,.5SQ	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.88
Is Samacsys：	N	JESD-30 代码：	S-PQCC-J28
JESD-609代码：	e0	长度：	11.505 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC28,.5SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	225	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	4.57 mm
子类别：	Other Telecom ICs	最大压摆率：	0.015 mA
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	11.505 mm	Base Number Matches：	1

MT8941AE 数据手册

CMOS ST-BUS FAMILY MT8941

Advanced T1/CEPT Digital Trunk PLL

ISSUE 5

July 1993

Features

Ordering Information

•

Provides T1 clock at 1.544 MHz locked to an 8

kHz reference clock (frame pulse)

MT8941AE

MT8941AP

24 Pin Plastic DIP

28 Pin PLCC

Provides CEPT clock at 2.048 MHz and ST-

BUS clock and timing signals locked to an

internal or external 8 kHz reference clock

-40°C to +85°C

•

Typical inherent output jitter (unfiltered)= 0.07

UI peak-to-peak

Description

Typical jitter attenuation at: 10 Hz=23 dB,100

Hz=43 dB, 5 to 40 kHz ≥ 64 dB

The MT8941 is a dual digital phase-locked loop

providing the timing and synchronization signals for

the T1 or CEPT transmission links and the ST-BUS.

The first PLL provides the T1 clock (1.544 MHz)

synchronized to the input frame pulse at 8 kHz. The

timing signals for the CEPT transmission link and the

ST-BUS are provided by the second PLL locked to

an internal or an external 8 kHz frame pulse signal.

•

Jitter-free “FREE-RUN” mode

Uncommitted two-input NAND gate

Low power CMOS technology

Applications

The MT8941 offers improved jitter performance over

the MT8940. The two devices also have some

functional differences, which are listed in the section

on “Differences between MT8941 and MT8940”.

•

Synchronization and timing control for T1

and CEPT digital trunk transmission links

ST- BUS clock and frame pulse source

CVb

F0i

Variable

DPLL #1

Clock

Control

2:1 MUX

C12i

ENCV

MS0

Frame Pulse

Control

Mode

Selection

Logic

MS1

MS2

F0b

Input

Selector

MS3

C4b

4.096 MHz

Clock

Control

C8Kb

C4o

ENC4o

C16i

DPLL #2

C2o

Clock

Generator

2.048 MHz

Clock

Control

C2o

ENC2o

V_DD

V_SS

RST

Figure 1 - Functional Block Diagram

3-43

12 3 4 5 6 7...18

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与MT8941AE相关器件

型号	品牌	描述	获取价格	数据表
MT8941AP	MITEL	CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital	获取价格
MT8941B	MITEL	CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital	获取价格
MT8941BE	MITEL	CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital	获取价格
MT8941BE	ZARLINK	Advanced T1/CEPT Digital Trunk PLL	获取价格
MT8941BE1	ZARLINK	Telecom Circuit, 1-Func, CMOS, PDIP24, LEAD FREE, PLASTIC, MS-011AA, DIP-24	获取价格
MT8941BP	MITEL	CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital	获取价格