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MT8952BP

更新时间: 2024-09-24 22:51:03
品牌 Logo 应用领域
MITEL 外围集成电路控制器
页数 文件大小 规格书
27页 172K
描述
ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller

MT8952BP 数据手册

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ISO-CMOS ST-BUS FAMILY MT8952B  
HDLC Protocol Controller  
ISSUE6  
March 1997  
Features  
Formats data as per X.25 (CCITT) level-2  
standards  
Ordering Information  
MT8952BE  
28 Pin Plastic DIP  
28 Pin PLCC  
Go-Ahead sequence generation and detection  
Single byte address recognition  
MT8952BP  
MT8952BS  
28 Pin SOIC  
Microprocessor port and directly accessible  
registers for flexible operation and control  
-40°C to 85°C  
19 byte FIFO in both send and receive paths  
Handshake signals for multiplexing data links  
High speed serially clocked output (2.5 Mbps)  
Description  
ST-BUS compatibility with programmable  
channel selection for data and separate  
timeslot for control information  
The MT8952B HDLC Protocol Controller frames and  
formats data packets according to X.25 (Level 2)  
Recommendations from the CCITT.  
Independent watchdog timer  
Facility to disable protocol functions  
Low power ISO-CMOS technology  
Applications  
Data link controllers and protocol generators  
Digital sets, PBXs and private packet networks  
D-channel controller for ISDN basic access  
C-channel controller to Digital Network  
Interface Circuits (typically MT8972)  
Interprocessor communication  
TEOP  
C-Channel  
Transmit  
Logic  
Zero  
Insertion  
Flag/Abort  
Generator  
Interface  
Transmit  
FIFO  
CDSTo  
D0-D7  
Micro  
F0i  
A0-A3  
R/W  
Control  
and Status  
Register  
Processor  
Interface  
CKi  
Interrupt  
Registers  
Address  
Decoder  
Timing  
Logic  
RxCEN  
TxCEN  
CS  
E
IRQ  
WD  
V
DD  
Flag/Abort/  
Idle  
Detection  
Receive  
FIFO  
Address  
Detection  
Zero  
Deletion  
CDSTi  
REOP  
Receive Logic  
V
SS  
RST  
Figure 1 - Functional Block Diagram  
3-61  

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