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MT8952BP1 PDF预览

MT8952BP1

更新时间: 2024-01-30 13:33:14
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 通信时钟数据传输外围集成电路
页数 文件大小 规格书
32页 414K
描述
Serial I/O Controller, 1 Channel(s), 0.3125MBps, CMOS, PQCC28, LEAD FREE, PLASTIC, MS-018AB, LCC-28

MT8952BP1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:LCC
包装说明:QCCJ, LDCC28,.5SQ针数:28
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:2.27地址总线宽度:4
边界扫描:NO总线兼容性:6800; 6809
最大时钟频率:5 MHz通信协议:SYNC, HDLC; X.25
数据编码/解码方法:NRZ最大数据传输速率:0.3125 MBps
外部数据总线宽度:8JESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.505 mm
低功率模式:NO串行 I/O 数:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Serial IO/Communication Controllers最大压摆率:1 mA
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:11.505 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches:1

MT8952BP1 数据手册

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ISO-CMOS ST-BUSTM Family  
MT8952B  
HDLC Protocol Controller  
Data Sheet  
August 2011  
Features  
Formats data as per X.25 (CCITT) level-2  
standards  
Ordering Information  
MT8952BE1  
MT8952BP1  
MT8952BPR1 28 Pin PLCC*  
28 Pin PDIP*  
28 Pin PLCC*  
Tubes  
Tubes  
Tape & Reel  
Tubes  
Go-Ahead sequence generation and detection  
Single byte address recognition  
MT8952BS1  
28 Pin SOIC*  
Microprocessor port and directly accessible  
registers for flexible operation and control  
*Pb Free Matte Tin  
-40C to +85C  
19 byte FIFO in both send and receive paths  
Handshake signals for multiplexing data links  
High speed serially clocked output (2.5 Mbps)  
Digital sets, PBXs and private packet networks  
D-channel controller for ISDN basic access  
ST-BUS compatibility with programmable channel  
selection for data and separate timeslot for  
control information  
C-channel controller to Digital Network Interface  
Circuits (typically MT8972)  
Independent watchdog timer  
Interprocessor communication  
Facility to disable protocol functions  
Low power ISO-CMOS technology  
Description  
The MT8952B HDLC Protocol Controller frames and  
formats data packets according to X.25 (Level 2)  
Recommendations from the CCITT.  
Applications  
Data link controllers and protocol generators  
TEOP  
C-Channel  
Transmit  
Logic  
Zero  
Insertion  
Flag/Abort  
Generator  
Interface  
Transmit  
FIFO  
CDSTo  
D0-D7  
Micro  
F0i  
A0-A3  
Control  
and Status  
Register  
Processor  
CKi  
Interrupt  
Registers  
Address  
Decoder  
Timing  
Logic  
R/W  
Interface  
RxCEN  
TxCEN  
CS  
E
IRQ  
WD  
VDD  
VSS  
Flag/Abort/  
Idle  
Detection  
Receive  
FIFO  
Address  
Detection  
Zero  
Deletion  
CDSTi  
REOP  
Receive Logic  
RST  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.  

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