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MT8952BP PDF预览

MT8952BP

更新时间: 2024-02-22 01:00:28
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 外围集成电路
页数 文件大小 规格书
26页 667K
描述
Serial I/O Controller, 1 Channel(s), 0.3125MBps, CMOS, PQCC28, PLASTIC, MS-018AB, LCC-28

MT8952BP 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:compliant
HTS代码:8542.31.00.01风险等级:5.72
Is Samacsys:N地址总线宽度:4
边界扫描:NO总线兼容性:6800; 6809
最大时钟频率:5 MHz通信协议:SYNC, HDLC; X.25
数据编码/解码方法:NRZ最大数据传输速率:0.3125 MBps
外部数据总线宽度:8JESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.505 mm
低功率模式:NO湿度敏感等级:1
串行 I/O 数:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Serial IO/Communication Controllers最大压摆率:1 mA
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:11.505 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches:1

MT8952BP 数据手册

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ISO-CMOS ST-BUSFAMILY MT8952B  
HDLC Protocol Controller  
ISSUE6  
March 1997  
Features  
Formats data as per X.25 (CCITT) level-2  
standards  
Ordering Information  
MT8952BE  
MT8952BP  
MT8952BS  
28 Pin Plastic DIP  
28 Pin PLCC  
28 Pin SOIC  
Go-Ahead sequence generation and detection  
Single byte address recognition  
Microprocessor port and directly accessible  
registers for flexible operation and control  
-40°C to 85°C  
19 byte FIFO in both send and receive paths  
Handshake signals for multiplexing data links  
High speed serially clocked output (2.5 Mbps)  
Description  
ST-BUS compatibility with programmable  
channel selection for data and separate  
timeslot for control information  
The MT8952B HDLC Protocol Controller frames and  
formats data packets according to X.25 (Level 2)  
Recommendations from the CCITT.  
Independent watchdog timer  
Facility to disable protocol functions  
Low power ISO-CMOS technology  
Applications  
Data link controllers and protocol generators  
Digital sets, PBXs and private packet networks  
D-channel controller for ISDN basic access  
C-channel controller to Digital Network  
Interface Circuits (typically MT8972)  
Interprocessor communication  
TEOP  
C-Channel  
Transmit  
Logic  
Zero  
Insertion  
Flag/Abort  
Generator  
Interface  
Transmit  
FIFO  
CDSTo  
D0-D7  
Micro  
F0i  
A0-A3  
R/W  
Control  
and Status  
Register  
Processor  
Interface  
CKi  
Interrupt  
Registers  
Address  
Decoder  
Timing  
Logic  
RxCEN  
TxCEN  
CS  
E
IRQ  
WD  
V
DD  
Flag/Abort/  
Idle  
Detection  
Receive  
FIFO  
Address  
Detection  
Zero  
Deletion  
CDSTi  
REOP  
Receive Logic  
V
SS  
RST  
Figure 1 - Functional Block Diagram  
3-61  

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