Datasheet > MT8940-1

MT8940-1

更新时间： 2022-12-12 10:54:22

品牌	Logo	应用领域
MITEL		/
页数	文件大小	规格书
19页	135K
描述
ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL

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MT8940-1 数据手册

ISO-CMOS ST-BUS FAMILY

T1/CEPT Digital Trunk PLL

MT8940

ISSUE 8

March 1997

Features

Ordering Information

•

Provides T1 clock at 1.544 MHz locked to input

frame pulse

MT8940AE

24 Pin Plastic DIP (600 mil)

Sources CEPT (30+2) Digital Trunk/ST-BUS

clock and timing signals locked to internal or

external 8 kHz signal

-40°C to +85°C

•

TTL compatible logic inputs and outputs

Uncommitted 2-input NAND gate

Single 5 volt power supply

Description

The MT8940 is a dual digital phase-locked loop

providing the timing and synchronization signals for

the T1 or CEPT transmission links and the ST-BUS.

The ﬁrst PLL provides the T1 clock (1.544 MHz)

synchronized to the input frame pulse at 8 kHz. The

timing signals for the CEPT transmission link and the

ST-BUS are provided by the second PLL locked to an

internal or an external 8 kHz frame pulse signal.

Low power ISO-CMOS technology

Applications

•

Synchronization and timing control for T1

and CEPT digital trunk transmission links

ST- BUS clock and frame pulse source

The MT8940 is fabricated in MITEL’s ISO-CMOS

technology.

CVb

F0i

Variable

DPLL #1

Clock

Control

2:1 MUX

C12i

ENCV

MS0

Frame Pulse

Control

Mode

Selection

Logic

MS1

MS2

F0b

Input

Selector

MS3

C4b

4.096 MHz

Clock

Control

C8Kb

C4o

ENC4o

C16i

DPLL #2

C2o

Clock

Generator

2.048 MHz

Clock

Control

C2o

ENC2o

RST

Figure 1 - Functional Block Diagram

3-27

12 3 4 5 6 7...19

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