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MT5C2564C-35/883C PDF预览

MT5C2564C-35/883C

更新时间: 2024-11-05 05:50:39
品牌 Logo 应用领域
AUSTIN 静态存储器
页数 文件大小 规格书
11页 126K
描述
SRAM

MT5C2564C-35/883C 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:DIP包装说明:0.300 INCH, CERAMIC, DIP-24
针数:24Reach Compliance Code:compliant
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.41
风险等级:5.11最长访问时间:35 ns
JESD-30 代码:R-CDIP-T24内存密度:262144 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
功能数量:1端子数量:24
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:64KX4
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified筛选级别:MIL-STD-883
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MT5C2564C-35/883C 数据手册

 浏览型号MT5C2564C-35/883C的Datasheet PDF文件第2页浏览型号MT5C2564C-35/883C的Datasheet PDF文件第3页浏览型号MT5C2564C-35/883C的Datasheet PDF文件第4页浏览型号MT5C2564C-35/883C的Datasheet PDF文件第5页浏览型号MT5C2564C-35/883C的Datasheet PDF文件第6页浏览型号MT5C2564C-35/883C的Datasheet PDF文件第7页 
SRAM  
MT5C2564  
Austin Semiconductor, Inc.  
64K x 4 SRAM  
SRAM MEMORY ARRAY  
PIN ASSIGNMENT  
(Top View)  
AVAILABLE AS MILITARY  
SPECIFICATIONS  
• SMD 5962-88681  
• MIL-STD-883  
24-Pin DIP (C)  
(300 MIL)  
28-Pin LCC (EC)  
FEATURES  
3
2 1 28 27  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Vcc  
• High Speed: 15, 20, 25, 35, 45, 55, and 70  
• Battery Backup: 2V data retention  
• Low power standby  
2 6  
2 5  
2 4  
2 3  
2 2  
2 1  
2 0  
1 9  
1 8  
A15  
A14  
A13  
A12  
A11  
A10  
DQ4  
DQ3  
DQ2  
A15  
A14  
A13  
A12  
A11  
A10  
DQ4  
DQ3  
DQ2  
DQ1  
WE\  
A2  
A3  
A4  
A5  
A6  
A7  
A8 1 0  
A9 1 1  
CE\ 1 2  
4
5
6
7
8
9
• High-performance, low-power, CMOS double-metal  
process  
• Single +5V (+10%) Power Supply  
• Easy memory expansion with CE\  
• All inputs and outputs are TTL compatible  
A9 10  
CE\ 11  
Vss 12  
13 14 15 16 17  
OPTIONS  
• Timing  
MARKING  
15ns access  
20ns access  
25ns access  
35ns access  
45ns access  
55ns access  
70ns access  
-15  
-20  
-25  
-35  
-45  
-55*  
-70*  
GENERAL DESCRIPTION  
The Austin Semiconductor SRAM family employs  
high-speed, low-power CMOS and are fabricated using double-  
layer metal, double-layer polysilicon technology.  
For flexibility in high-speed memory applications,  
Austin Semiconductor offers chip enable (CE\) on all organiza-  
tions. This enhancement can place the outputs in High-Z for  
additional flexibility in system design. The x4 configuration  
features common data input and output.  
Writing to these devices is accomplished when write  
enable (WE\) and CE\ inputs are both LOW. Reading is accom-  
plished when WE\ remains HIGH and CE\ goes LOW. The  
device offers a reduced power standby mode when disabled.  
This allows system designs to achieve low standby power re-  
quirements.  
• Package(s)  
Ceramic DIP (300 mil)  
CeramicLCC  
C
EC  
No. 106  
No. 204  
• Operating Temperature Ranges  
Industrial (-40oC to +85oC)  
Military (-55oC to +125oC)  
IT  
XT  
• 2V data retention/low power  
L
*Electrical characteristics identical to those provided for the 45ns  
access devices.  
These devices operate from a single +5V power sup-  
ply and all inputs and outputs are fully TTL compatible.  
For more products and information  
please visit our web site at  
www.austinsemiconductor.com  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2564  
Rev. 2.0 11/00  
1

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