1Mb: 64K x 18, 32K x 32/36
3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
MT58L64L18F, MT58L32L32F,
MT58L32L36F
1Mb SYNCBURST™
SRAM
3.3V VDD, 3.3V I/O, Flow-Through
FEATURES
• Fast clock and OE# access times
100-Pin TQFP*
• Single +3.3V +0.3V/-0.165V power supply (VDD)
• Separate +3.3V +0.3V/-0.165V isolated output buffer
supply (VDDQ)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion and
address pipelining
• Clock-controlled and registered addresses, data I/Os
and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down for portable applications
• 100-lead TQFP package for high density, high speed
• Low capacitive bus loading
*JEDEC-standard MS-026 BHA (LQFP).
• x18, x32 and x36 versions available
OPTIONS
MARKING
(CLK). The synchronous inputs include all addresses, all
data inputs, active LOW chip enable (CE#), two additional
chip enables for easy depth expansion (CE2, CE2#), burst
controlinputs(ADSC#, ADSP#, ADV#), bytewriteenables
(BWx#) and global write (GW#).
Asynchronous inputs include the output enable (OE#),
snooze enable (ZZ) and clock (CLK). There is also a burst
mode pin (MODE) that selects between interleaved and
linear burst modes. The data-out (Q), enabled by OE#, is
also asynchronous. WRITE cycles can be from one to two
bytes wide (x18) or from one to four bytes wide (x32/x36),
as controlled by the write control inputs.
Burstoperationcanbeinitiatedwitheitheraddressstatus
processor (ADSP#) or address status controller (ADSC#)
input pins. Subsequent burst addresses can be internally
generated as controlled by the burst advance pin (ADV#).
Address and write control are registered on-chip to
simplifyWRITEcycles.Thisallowsself-timedWRITEcycles.
Individualbyteenablesallowindividualbytestobewritten.
During WRITE cycles on the x18 device, BWa# controls
DQa pins and DQPa; BWb# controls DQb pins and DQPb.
During WRITE cycles on the x32 and x36 devices, BWa#
controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb; BWc# controls DQc pins and DQPc; BWd# controls
DQd pins and DQPd. GW# LOW causes all bytes to be
written. Parity bits are only available on the x18 and x36
versions.
• Timing (Access/Cycle/MHz)
7.5ns/8.8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
-7.5
-8.5
-10
• Configurations
64K x 18
MT58L64L18F
MT58L32L32F
MT58L32L36F
32K x 32
32K x 36
• Package
100-pin TQFP
T
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
None
IT
• Part Number Example: MT58L32L36FT-10 IT
GENERAL DESCRIPTION
The Micron SyncBurst SRAM family employs high-
speed, low-power CMOS designs that are fabricated using
an advanced CMOS process.
The MT58L64L18F and MT58L32L32/36F 1Mb SRAMs
integrate a 64K x 18, 32K x 32, or 32K x 36 SRAM core with
advanced synchronous peripheral circuitry and a 2-bit
burstcounter.Allsynchronousinputspassthroughregisters
controlled by a positive-edge-triggered single clock input
®
™
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM
MT58L64L18F.p65 – Rev. 9/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
All registered and unregistered trademarks are the sole property of their respective companies.
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