Datasheet > MT58L32L32PT-7.5T

MT58L32L32PT-7.5T

更新时间： 2024-11-07 14:53:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
17页	239K
描述
Cache SRAM, 32KX32, 4.2ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

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MT58L32L32PT-7.5T 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.6
Is Samacsys：	N	最长访问时间：	4.2 ns
其他特性：	PIPELINED ARCHITECTURE	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	内存密度：	1048576 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	32
功能数量：	1	端子数量：	100
字数：	32768 words	字数代码：	32000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	32KX32
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

MT58L32L32PT-7.5T 数据手册

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1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, SCD SYNCBURST SRAM

MT58L64L18P, MT58L32L32P,

MT58L32L36P

3.3V VDD, 3.3V I/O, Pipelined, Single-Cycle

Deselect

1Mb SYNCBURST^™

SRAM

FEATURES

• Fast clock and OE# access times

• Single +3.3V +0.3V/ -0.165V power supply (V^DD)

• Separate +3.3V +0.3V/ -0.165V isolated output buffer

supply (VDDQ)

100-Pin TQFP**

(D-1)

• SNOOZE MODE for reduced-power standby

• Single-cycle deselect (Pentium BSRAM-compatible)

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL WRITE

• Three chip enables for simple depth expansion and

address pipelining

• Clock-controlled and registered addresses, data I/ Os

and control signals

• Internally self-timed WRITE cycle

• Burst control pin (interleaved or linear burst)

• Automatic power-down for portable applications

• 100-lead TQFP for high density, high speed

• Low capacitive bus loading

**JEDEC-standard MS-026 BHA (LQFP).

• x18, x32 and x36 options available

controlled by a positive-edge-triggered single clock input

(CLK). The synchronous inputs include all addresses, all

data inputs, active LOW chip enable (CE#), two additional

chip enables for easy depth expansion (CE2, CE2#), burst

control inputs (ADSC#, ADSP#, ADV#), byte write enables

(BWx#) and global write (GW#).

OPTIONS

MARKING

• Timing (Access/ Cycle/ MHz)

3.5ns/ 6.0ns/ 166 MHz

4.2ns/ 7.5ns/ 133 MHz

5ns/ 10ns/ 100 MHz

-6

-7.5

-10

Asynchronous inputs include the output enable (OE#),

clock (CLK) and snooze enable (ZZ). There is also a burst

mode pin (MODE) that selects between interleaved and

linear burst modes. The data-out (Q), enabled by OE#, is

also asynchronous. WRITE cycles can be from one to two

bytes wide (x18) or from one to four bytes wide (x32/ x36),

as controlled by the write control inputs.

• Configurations

64K x 18

MT58L64L18P

MT58L32L32P

MT58L32L36P

32K x 32

32K x 36

• Package

100-pin TQFP

Burst operation can be initiated with either address status

processor (ADSP#) or address status controller (ADSC#)

input pins. Subsequent burst addresses can be internally

generated as controlled by the burst advance pin (ADV#).

Address and write control are registered on-chip to

simplify WRITEcycles.Thisallowsself-timed WRITEcycles.

Individualbyte enables allow individualbytes to be written.

During WRITE cycles on the x18 device, BWa# controls

DQa pins and DQPa; BWb# controls DQb pins and DQPb.

During WRITE cycles on the x32 and x36 devices, BWa#

controls DQa pins and DQPa; BWb# controls DQb pins and

DQPb; BWc# controls DQc pins and DQPc; BWd# controls

DQd pins and DQPd. GW# LOW causes all bytes to be

written. Parity pins are only available on the x18 and x36

versions.

• Temperature

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

None

• Part Number Example: MT58L64L18PT-10 T

*Under consideration.

GENERAL DESCRIPTION

™

The Micron SyncBurst SRAM family employs high-

speed, low-power CMOS designs that are fabricated using

an advanced CMOS process.

The MT58L64L18P and MT58L32L32/ 36P 1Mb SRAMs

integrate a 64K x 18, 32K x 32, or 32K x 36 SRAM core with

advanced synchronous peripheral circuitry and a 2-bit

burst counter.Allsynchronousinputspassthrough registers

1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, SCD SyncBurst SRAM

MT58L64L18P.p65 – Rev. 6/99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1999, Micron Technology, Inc.

All registered and unregistered trademarks are the sole property of their respective companies.

12 3 4 5 6 7...17

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与MT58L32L32PT-7.5T相关器件

型号	品牌	获取价格	描述	数据表
MT58L32L36DT-10	CYPRESS	获取价格	Cache SRAM, 32KX36, 5ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58L32L36DT-7.5	CYPRESS	获取价格	Cache SRAM, 32KX36, 4.2ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58L32L36FT-10	CYPRESS	获取价格	Cache SRAM, 32KX36, 10ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L32L36FT-10IT	CYPRESS	获取价格	Cache SRAM, 32KX36, 10ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L32L36FT-8.5	CYPRESS	获取价格	Cache SRAM, 32KX36, 8.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L32L36FT-8.5IT	CYPRESS	获取价格	Cache SRAM, 32KX36, 8.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L32L36PT-10T	CYPRESS	获取价格	Cache SRAM, 32KX36, 5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100
MT58L32L36PT-6	CYPRESS	获取价格	Cache SRAM, 32KX36, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58L512L18D	MICRON	获取价格	8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
MT58L512L18DB-10IT	CYPRESS	获取价格	Standard SRAM, 512KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119

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