Datasheet > MT58L32L32PT-7.5

MT58L32L32PT-7.5

更新时间： 2024-11-08 04:51:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
18页	354K
描述
Cache SRAM, 32KX32, 4.2ns, CMOS, PQFP100, PLASTIC, TQFP-100

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中文翻译

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数据手册

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MT58L32L32PT-7.5 数据手册

NOTRECOMENDEDFORNEWDESIGNS

1Mb: 64K x 18, 32K x 32/36

3.3V I/O, PIPELINED, SCD SYNCBURST SRAM

1Mb SYNCBURST^™

SRAM

MT58L64L18P, MT58L32L32P,

MT58L32L36P

3.3V VDD, 3.3V I/O, Pipelined, Single-

Cycle Deselect

FEATURES

• Fast clock and OE# access times

• Single +3.3V +0.3V/-0.165V power supply (V^DD)

• Separate +3.3V +0.3V/-0.165V isolated output

buffer supply (VDDQ)

100-Pin TQFP*

• SNOOZE MODE for reduced-power standby

• Single-cycle deselect (Pentium^®BSRAM-

compatible)

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL

WRITE

• Three chip enables for simple depth expansion

and address pipelining

• Clock-controlled and registered addresses, data

I/Os and control signals

• Internally self-timed WRITE cycle

• Burst control pin (interleaved or linear burst)

• Automatic power-down for portable applications

• 100-lead TQFP for high density, high speed SRAMs

• Low capacitive bus loading

*JEDEC-standard MS-026 BHA (LQFP).

through registers controlled by a positive-edge-trig-

gered single clock input (CLK). The synchronous in-

puts include all addresses, all data inputs, active LOW

chip enable (CE#), two additional chip enables for easy

depth expansion (CE2, CE2#), burst control inputs

(ADSC#, ADSP#, ADV#), byte write enables (BWx#) and

global write (GW#).

Asynchronous inputs include the output enable

(OE#), clock (CLK) and snooze enable (ZZ). There is

also a burst mode pin (MODE) that selects between

interleaved and linear burst modes. The data-out (Q),

enabled by OE#, is also asynchronous. WRITE cycles

can be from one to two bytes wide (x18) or from one to

four bytes wide (x32/x36), as controlled by the write

control inputs.

• x18, x32, and x36 options available

OPTIONS

MARKING

• Timing (Access/Cycle/MHz)

3.5ns/6.0ns/166 MHz

4.2ns/7.5ns/133 MHz

5ns/10ns/100 MHz

• Configurations

64K x 18

-6

-7.5

-10

MT58L64L18P

MT58L32L32P

MT58L32L36P

32K x 32

32K x 36

• Package

100-pin TQFP

• Operating Temperature Range

Commercial (0ºC to +70ºC)

None

Burst operation can be initiated with either address

status processor (ADSP#) or address status controller

(ADSC#) input pins. Subsequent burst addresses can

be internally generated as controlled by the burst ad-

vance pin (ADV#).

Part Number Example:

MT58L64L18PT-10

GENERALDESCRIPTION

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE

cycles. Individual byte enables allow individual bytes

to be written. During WRITE cycles on the x18 device,

BWa# controls DQa pins and DQPa; BWb# controls DQb

pins and DQPb. During WRITE cycles on the x32 and

x36 devices, BWa# controls DQa pins and DQPa; BWb#

controls DQb pins and DQPb; BWc# controls DQc pins

The Micron^®SyncBurst^™SRAM family employs

high-speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

The MT58L64L18P and MT58L32L32/36P 1Mb

SRAMs integrate a 64K x 18, 32K x 32, or 32K x 36 SRAM

core with advanced synchronous peripheral circuitry

and a 2-bit burst counter. All synchronous inputs pass

1Mb:64Kx18, 32Kx32/363.3VI/O, Pipelined, SCDSyncBurstSRAM

MT58L64L18P_B.p65 – Rev. B, Pub. 11/02

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

12 3 4 5 6 7...18

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与MT58L32L32PT-7.5相关器件

型号	品牌	获取价格	描述	数据表
MT58L32L32PT-7.5T	CYPRESS	获取价格	Cache SRAM, 32KX32, 4.2ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100
MT58L32L36DT-10	CYPRESS	获取价格	Cache SRAM, 32KX36, 5ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58L32L36DT-7.5	CYPRESS	获取价格	Cache SRAM, 32KX36, 4.2ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58L32L36FT-10	CYPRESS	获取价格	Cache SRAM, 32KX36, 10ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L32L36FT-10IT	CYPRESS	获取价格	Cache SRAM, 32KX36, 10ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L32L36FT-8.5	CYPRESS	获取价格	Cache SRAM, 32KX36, 8.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L32L36FT-8.5IT	CYPRESS	获取价格	Cache SRAM, 32KX36, 8.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L32L36PT-10T	CYPRESS	获取价格	Cache SRAM, 32KX36, 5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100
MT58L32L36PT-6	CYPRESS	获取价格	Cache SRAM, 32KX36, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58L512L18D	MICRON	获取价格	8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

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