NOTRECOMENDEDFORNEWDESIGNS
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
1Mb SYNCBURST™
SRAM
MT58L64L18D, MT58L32L32D,
MT58L32L36D
3.3V VDD, 3.3V I/O, Pipelined, Double-
Cycle Deselect
FEATURES
• Fast clock and OE# access times
100-Pin TQFP*
• Single +3.3V +0.3V/-0.165V power supply (VDD)
• Separate +3.3V +0.3V/-0.165V isolated output
buffer supply (VDDQ)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion
and address pipelining
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down for portable applications
• 100-lead TQFP package for high density, high
speed SRAMs
*JEDEC-standard MS-026 BHA (LQFP).
• Low capacitive bus loading
• x18, x32, and x36 options available
gered single clock input (CLK). The synchronous in-
puts include all addresses, all data inputs, active LOW
chip enable (CE#), two additional chip enables for easy
depth expansion (CE2, CE2#), burst control inputs
(ADSC#, ADSP#, ADV#), byte write enables (BWx#) and
global write (GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is
also a burst mode pin (MODE) that selects between
interleaved and linear burst modes. The data-out (Q),
enabled by OE#, is also asynchronous. WRITE cycles
can be from one to two bytes wide (x18) or from one to
four bytes wide (x32/x36), as controlled by the write
control inputs.
OPTIONS
MARKING
• Timing (Access/Cycle/MHz)
3.5ns/6.0ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
-6
-7.5
-10
• Configurations
64K x 18
MT58L64L18D
MT58L32L32D
MT58L32L36D
32K x 32
32K x 36
• Package
100-pin TQFP
T
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can
be internally generated as controlled by the burst ad-
vance pin (ADV#).
None
Part Number Example:
MT58L64L18DT-10
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls DQb
pins and DQPb. During WRITE cycles on the x32 and
x36 devices, BWa# controls DQa pins and DQPa; BWb#
controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. GW#
LOW causes all bytes to be written. Parity pins are only
GENERALDESCRIPTION
The Micron® SyncBurst™ SRAM family employs
high- speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
The MT58L64L18D and MT58L32L32/36D 1Mb
SRAMs integrate a 64K x 18, 32K x 32, or 32K x 36 SRAM
core with advanced synchronous peripheral circuitry
and a 2-bit burst counter. All synchronous inputs pass
through registers controlled by a positive-edge-trig-
1Mb:64Kx18, 32Kx32/363.3VI/O, Pipelined, DCDSyncBurstSRAM
MT58L64L18D_B.p65 – Rev. B, Pub. 11/02
©2002,MicronTechnology,Inc.
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.