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MT58L128L36P1T-5IT PDF预览

MT58L128L36P1T-5IT

更新时间： 2024-02-26 18:19:24
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
27页 447K
描述
Cache SRAM, 128KX36, 3.1ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

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MT58L128L36P1T-5IT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP,
针数：100Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.44最长访问时间：3.1 ns
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：4718592 bit
内存集成电路类型：CACHE SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX36封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

MT58L128L36P1T-5IT 数据手册

 浏览型号MT58L128L36P1T-5IT的Datasheet PDF文件第4页浏览型号MT58L128L36P1T-5IT的Datasheet PDF文件第5页浏览型号MT58L128L36P1T-5IT的Datasheet PDF文件第6页浏览型号MT58L128L36P1T-5IT的Datasheet PDF文件第8页浏览型号MT58L128L36P1T-5IT的Datasheet PDF文件第9页浏览型号MT58L128L36P1T-5IT的Datasheet PDF文件第10页 
PRELIMINARY  
4Mb : 256K x 18, 128K x 32/36  
PIPELINED, SCD SYNCBURST SRAM  
TQFP PIN DESCRIPTIONS (co n t in u e d )  
x18  
x32/x36  
SYMBOL TYPE  
DESCRIPTION  
85  
85  
ADSC#  
Input Synchronous Address Status Controller: This active LOW input  
interrupts any ongoing burst, causing a new external address to be  
registered. A READ or WRITE is performed using the new address if  
CE# is LOW. ADSC# is also used to place the chip into power-down  
state when CE# is HIGH.  
31  
64  
31  
64  
MODE  
ZZ  
Input Mode: This input selects the burst sequence. A LOW on this pin  
selects “linear burst.” NC or HIGH on this pin selects “interleaved  
burst.” Do not alter input state while device is operating.  
Input Snooze Enable: This active HIGH, asynchronous input causes the  
device to enter a low-power standby mode in which all data in the  
memory array is retained. When ZZ is active, all other inputs are  
ignored.  
(a) 58, 59,  
62, 63, 68, 69, 56-59, 62, 63  
72, 73  
(b) 8, 9, 12,  
13, 18, 19, 22, 72-75, 78, 79  
(a) 52, 53,  
DQa  
DQb  
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b”  
Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins;  
Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins.  
Input data must meet setup and hold times around the rising edge  
of CLK.  
(b) 68, 69  
23  
(c) 2, 3, 6-9,  
12, 13  
(d) 18, 19,  
22-25, 28, 29  
DQc  
DQd  
74  
24  
–
51  
80  
1
NC/DQPa  
NC/DQPb  
NC/DQPc  
NC/DQPd  
NC/  
I/O  
No Connect/Parity Data I/Os: On the x32 version, these pins are No  
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”  
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte  
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.  
–
30  
14, 15, 41, 65, 14, 15, 41, 65,  
91 91  
V
DD  
Supply Power Supply: See DC Electrical Characteristics and Operating  
Conditions for range.  
4, 11, 20, 27, 4, 11, 20, 27,  
54, 61, 70, 77 54, 61, 70, 77  
V
DD  
Q
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and  
Operating Conditions for range.  
5, 10, 17, 21, 5, 10, 17, 21,  
26, 40, 55, 60, 26, 40, 55, 60,  
67, 71, 76, 90 67, 71, 76, 90  
V
SS  
Supply Ground: GND.  
38, 39  
38, 39  
DNU  
NC  
–
–
Do Not Use: These signals may either be unconnected or wired to  
GND to improve package heat dissipation.  
1-3, 6, 7, 16,  
25, 28-30,  
16, 66  
No Connect: These signals are not internally connected and may be  
connected to ground to improve package heat dissipation.  
51-53, 56, 57,  
66, 75, 78, 79,  
95, 96  
42, 43  
42, 43  
NF  
–
No Function: These pins are internally connected to the die and  
have the capacitance of input pins. It is allowable to leave these  
pins unconnected or driven by signals. Reserved for address  
expansion; pin 43 becomes an SA at 8Mb density and pin 42  
becomes an SA at 16Mb density.  
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM  
MT58L256L18P1.p65 – Rev. 3/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
6
©2000, Micron Technology, Inc.  
1...45678910...27

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