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MT58L128L18DT-10IT PDF预览

MT58L128L18DT-10IT

更新时间： 2024-02-23 04:58:33
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
17页 308K
描述
Cache SRAM, 128KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

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MT58L128L18DT-10IT 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.45
最长访问时间：5 nsJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：2359296 bit
内存集成电路类型：CACHE SRAM内存宽度：18
功能数量：1端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX18
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

MT58L128L18DT-10IT 数据手册

 浏览型号MT58L128L18DT-10IT的Datasheet PDF文件第5页浏览型号MT58L128L18DT-10IT的Datasheet PDF文件第6页浏览型号MT58L128L18DT-10IT的Datasheet PDF文件第7页浏览型号MT58L128L18DT-10IT的Datasheet PDF文件第9页浏览型号MT58L128L18DT-10IT的Datasheet PDF文件第10页浏览型号MT58L128L18DT-10IT的Datasheet PDF文件第11页 
2Mb: 128K x 18, 64K x 32/36  
PIPELINED, DCD SYNCBURST SRAM  
TRUTH TABLE  
OPERATION  
ADDRESS CE# CE2# CE2 ZZ ADSP# ADSC# ADV# WRITE# OE#  
USED  
CLK  
DQ  
Deselected Cycle, Power-Down None  
Deselected Cycle, Power-Down None  
Deselected Cycle, Power-Down None  
Deselected Cycle, Power-Down None  
Deselected Cycle, Power-Down None  
H
X
X
H
X
H
X
L
X
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H High-Z  
L-H High-Z  
L-H High-Z  
L-H High-Z  
L-H High-Z  
L
L
L
L
X
L
L
L
H
H
X
L
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
SNOOZE MODE, Power-Down  
READ Cycle, Begin Burst  
None  
External  
External  
External  
External  
External  
Next  
X
L
X
X
X
L
X
High-Z  
Q
L-H  
READ Cycle, Begin Burst  
L
L
L
H
X
L
L-H High-Z  
WRITE Cycle, Begin Burst  
READ Cycle, Begin Burst  
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H  
L-H  
D
Q
L
L
L
H
H
H
H
H
H
L
READ Cycle, Begin Burst  
L
L
L
H
L
L-H High-Z  
L-H  
L-H High-Z  
L-H  
L-H High-Z  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
WRITE Cycle, Continue Burst  
WRITE Cycle, Continue Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
WRITE Cycle, Suspend Burst  
WRITE Cycle, Suspend Burst  
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next  
L
H
L
Next  
L
Q
Next  
L
H
X
X
L
Next  
L
L-H  
L-H  
L-H  
D
D
Q
Next  
L
L
Current  
Current  
Current  
Current  
Current  
Current  
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H High-Z  
L-H  
L-H High-Z  
Q
H
X
X
L-H  
L-H  
D
D
L
NOTE: 1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.  
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE#  
are LOW or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.  
3. BWa# enables WRITEs to DQa pins, DQPa. BWb# enables WRITEs to DQb pins, DQPb. BWc# enables  
WRITEs to DQc pins, DQPc. BWd# enables WRITEs to DQd pins, DQPd. DQPa and DQPb are only  
available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version.  
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of  
CLK.  
5. Wait states are inserted by suspending burst.  
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and  
held HIGH throughout the input data hold time.  
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.  
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting  
one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK.  
Refer to WRITE timing diagram for clarification.  
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM  
MT58L128L18D.p65 – Rev. 9/99  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
1999, Micron Technology, Inc.  
8
1...567891011...17

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