Datasheet > MT58L128L18DT-10T

MT58L128L18DT-10T

更新时间： 2023-12-18 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
17页	302K
描述
Cache SRAM, 128KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

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MT58L128L18DT-10T 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP,
针数：	100	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.45	最长访问时间：	5 ns
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	2359296 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	128KX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

MT58L128L18DT-10T 数据手册

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2Mb: 128K x 18, 64K x 32/36

PIPELINED, DCD SYNCBURST SRAM

MT58L128L18D, MT58L64L32D,

MT58L64L36D

2Mb SYNCBURST^™

SRAM

3.3V VDD, 3.3V I/O, Pipelined, Double-Cycle Deselect

FEATURES

• Fast clock and OE# access times

100-Pin TQFP**

• Single +3.3V +0.3V/-0.165V power supply (V^DD)

• Separate +3.3V isolated output buffer supply (VDDQ)

• SNOOZE MODE for reduced-power standby

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL WRITE

• Three chip enables for simple depth expansion and

address pipelining

(D-1)

• Clock-controlled and registered addresses, data I/Os

and control signals

• Internally self-timed WRITE cycle

• Burst control pin (interleaved or linear burst)

• Automatic power-down for portable applications

• 100-lead TQFP package for high density, high speed

• Low capacitive bus loading

• x18, x32 and x36 options available

**JEDEC-standard MS-026 BHA (LQFP).

OPTIONS

MARKING

• Timing (Access/Cycle/MHz)

3.5ns/6ns/166 MHz

4.2ns/7.5ns/133 MHz

5ns/10ns/100 MHz

synchronous inputs include all addresses, all data inputs,

active LOW chip enable (CE#), two additional chip enables

for easy depth expansion (CE2, CE2#), burst control inputs

(ADSC#, ADSP#, ADV#), byte write enables (BWx#) and

global write (GW#).

Asynchronous inputs include the output enable (OE#),

clock (CLK) and snooze enable (ZZ). There is also a burst

mode pin (MODE) that selects between interleaved and

linear burst modes. The data-out (Q), enabled by OE#, is

also asynchronous. WRITE cycles can be from one to two

bytes wide (x18) or from one to four bytes wide (x32/x36),

as controlled by the write control inputs.

Burstoperationcanbeinitiatedwitheitheraddressstatus

processor (ADSP#) or address status controller (ADSC#)

input pins. Subsequent burst addresses can be internally

generated as controlled by the burst advance pin (ADV#).

Address and write control are registered on-chip to

simplifyWRITEcycles.Thisallowsself-timedWRITEcycles.

Individualbyteenablesallowindividualbytestobewritten.

During WRITE cycles on the x18 device, BWa# controls

DQa pins and DQPa; BWb# controls DQb pins and DQPb.

During WRITE cycles on the x32 and x36 devices, BWa#

controls DQa pins and DQPa; BWb# controls DQb pins and

DQPb; BWc# controls DQc pins and DQPc; BWd# controls

DQd pins and DQPd. GW# LOW causes all bytes to be

written. Parity pins are only available on the x18 and x36

versions.

-6

-7.5

-10

• Configurations

128K x 18

MT58L128L18D

MT58L64L32D

MT58L64L36D

64K x 32

64K x 36

• Package

100-pin TQFP

• Operating Temperature Range

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

None

• Part Number Example: MT58L128L18DT-10 T

*Under consideration.

GENERAL DESCRIPTION

™

The Micron SyncBurst SRAM family employs high-

speed, low-power CMOS designs that are fabricated using

an advanced CMOS process.

Micron’s 2Mb SyncBurst SRAMs integrate a 128K x 18,

64Kx32,or64Kx36SRAMcorewithadvancedsynchronous

peripheral circuitry and a 2-bit burst counter. All

synchronous inputs pass through registers controlled by a

positive-edge-triggered single clock input (CLK). The

2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM

MT58L128L18D.p65 – Rev. 7/99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1999, Micron Technology, Inc.

All registered and unregistered trademarks are the sole property of their respective companies.

12 3 4 5 6 7...17

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与MT58L128L18DT-10T相关器件

型号	品牌	获取价格	描述	数据表
MT58L128L18DT-6IT	CYPRESS	获取价格	Cache SRAM, 128KX18, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L128L18DT-6T	CYPRESS	获取价格	Standard SRAM, 128KX18, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100
MT58L128L18DT-7.5IT	CYPRESS	获取价格	Cache SRAM, 128KX18, 4ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L128L18DT-7.5T	CYPRESS	获取价格	Standard SRAM, 128KX18, 4ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100
MT58L128L18F	MICRON	获取价格	2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM
MT58L128L18FF-10	CYPRESS	获取价格	Standard SRAM, 128KX18, 10ns, CMOS, PBGA165, FBGA-165
MT58L128L18FF-6.8	CYPRESS	获取价格	Standard SRAM, 128KX18, 6.8ns, CMOS, PBGA165, FBGA-165
MT58L128L18FF8.5	CYPRESS	获取价格	128KX18 STANDARD SRAM, 8.5ns, PBGA165, FBGA-165
MT58L128L18FF-8.5	CYPRESS	获取价格	Standard SRAM, 128KX18, 8.5ns, CMOS, PBGA165, FBGA-165
MT58L128L18FT-10	MICRON	获取价格	2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM

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