Datasheet > MPC962308EJ-1HR2

MPC962308EJ-1HR2

更新时间： 2024-11-12 21:20:27

品牌	Logo	应用领域
恩智浦 - NXP		驱动光电二极管输出元件逻辑集成电路
页数	文件大小	规格书
12页	409K
描述
962308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, TSSOP-16

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MPC962308EJ-1HR2 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	16
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.08	系列：	962308
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	5 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	湿度敏感等级：	3
功能数量：	1	反相输出次数：
端子数量：	16	实输出次数：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.2 ns
座面最大高度：	1.2 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	4.4 mm
最小 fmax：	133.3 MHz	Base Number Matches：	1

MPC962308EJ-1HR2 数据手册

Freescale Semiconductor, Inc.

MOTOROLA

Order number: MPC962308

Rev 3, 08/2004

SEMICONDUCTOR TECHNICAL DATA

3.3 V Zero Delay Buffer

MPC962308

The MPC962308 is a 3.3 V Zero Delay Buffer designed to distribute

high-speed clocks in PC, workstation, datacom, telecom and other

high-performance applications. The MPC962308 uses an internal PLL and an

external feedback path to lock its low-skew clock output phase to the reference

clock phase, providing virtually zero propagation delay. The input-to-output

skew is guaranteed to be less than 250 ps and output-to-output skew is

guaranteed to be less than 200 ps.

Features

D SUFFIX

16-LEAD SOIC PACKAGE

CASE 751B-05

•

1:8 outputs LVCMOS zero-delay buffer

Zero input-output propagation delay, adjustable by the capacitive load on

FBK input

•

Multiple Configurations, see Table 2. Available MPC962308

Configurations

•

Multiple low-skew outputs

200 ps max output-output skew

700 ps max device-device skew

Two banks of four outputs, output tristate control by two select inputs

Supports a clock I/O frequency range of 10 MHz to 133 MHz

Low jitter, 200 ps max cycle-cycle (-1, -1H, -4, -5H)

±250 ps static phase offset (SPO)

DT SUFFIX

16-LEAD TSSOP PACKAGE

CASE 948F-01

16-pin SOIC package or 16-pin TSSOP package

Single 3.3 V supply

Ambient temperature range: –40°C to +85°C

Compatible with the CY2308 and CY23S08

Spread spectrum compatible

Functional Description

The MPC962308 has two banks of four outputs each which can be controlled by the select inputs as shown in Table 1. Select

Input Decoding. Bank B can be tristated if all of the outputs are not required. The select inputs also allow the input clock to be directly

applied to the output for chip and system testing purposes. The MPC962308 PLL enters a power down state when there are no rising

edges on the REF input. During this state, all of the outputs are in tristate and there is less than 50 µA of current draw. The PLL shuts

down in two additional cases explained in Table 1. Select Input Decoding.

Multiple MPC962308 devices can accept and distribute the same input clock throughout the system. In this situation, the difference

between the output skews of two devices will be less than 700 ps.

The MPC962308 is available in five different configurations as shown in Table 2. Available MPC962308 Configurations. In the

MPC962308-1, the reference frequency is reproduced by the PLL and provided at the outputs. A high drive version of this configura-

tion, the MPC962308-1H, is available to provide faster rise and fall times of the device.

The MPC962308-2 provides 2X and 1X the reference frequency at the output banks. In addition, the MPC962308-3 provides 4X

and 2X the reference frequency at the output banks. The output banks driving the feedback will determine the different configurations

of the above devices. The MPC962308-4 provides outputs 2X the reference frequency.The MPC962308-5H is a high drive version

with outputs of REF/2.

The MPC962308 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS

signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines on the

incident edge. Depending on the configuration, the device is offered in a 16-lead SOIC or 16-lead TSSOP package.

For More Information On This Product,

Go to: www.freescale.com

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与MPC962308EJ-1HR2相关器件

型号	品牌	获取价格	描述	数据表
MPC962309	MOTOROLA	获取价格	Low-Cost 3.3 V Zero Delay Buffer
MPC962309D-1	MOTOROLA	获取价格	Low-Cost 3.3 V Zero Delay Buffer
MPC962309D-1	IDT	获取价格	Low-Cost, 3.3V Zero Delay Buffer
MPC962309D-1	NXP	获取价格	IC,1:9 OUTPUT,SOP,16PIN,PLASTIC
MPC962309D-1H	IDT	获取价格	Low-Cost, 3.3V Zero Delay Buffer
MPC962309D-1H	MOTOROLA	获取价格	Low-Cost 3.3 V Zero Delay Buffer
MPC962309D-1H	NXP	获取价格	IC,1:9 OUTPUT,SOP,16PIN,PLASTIC
MPC962309D-1HR2	IDT	获取价格	Low-Cost, 3.3V Zero Delay Buffer
MPC962309D-1HR2	NXP	获取价格	962309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, 0.1
MPC962309D-1HR2	MOTOROLA	获取价格	Low-Cost 3.3 V Zero Delay Buffer

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