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MPC860UM

更新时间： 2024-09-22 22:51:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		PC
页数	文件大小	规格书
4页	213K
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Errata to the MPC860 PowerQUICC⑩ Family User’s Manual, Rev. 2

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MPC860UM 数据手册

Freescale Semiconductor, Inc.

Addendum

MPC860UMAD

Rev. 2.4, 4/2004

Errata to the MPC860

PowerQUICC™ Family

User’s Manual, Rev. 2

This errata describes corrections to Revision 2 of the MPC860 PowerQUICC™ Family User’s

Manual (Order No. MPC860UM, Rev. 2).

The MPC860 is a PowerPC™ architecture-based quad integrated communications controller

(PowerQUICC™). The CPU on the MPC860 is the MPC8xx core, a 32-bit microprocessor

that implements the PowerPC architecture, incorporating memory management units

(MMUs) and instruction and data caches.

1 Document Revision History

Table 1 provides a revision history for this document.

Table 1. Document Revision History

Rev. No.

Substantive Change(s)

2.2

Added new errata items from Section 12.5 (page 12-27), Section 27.8 (page 27-13,

27-14), Section 27.22 (page 27-29), Section 31.4.1.2 (page 30-9, 30-10), and Section

34.2.1 (page 34-4).

2.3

2.4

Added new errata item from Section 32.4.3 (page 32-8).

Added new errata items for Section 22 (page 22-1), Section 22.16 (page 22-15), Section

31.4.1.2 (page 30-9), and Section B.3.1 (page B-4)

2 Document Errata

The section and page numbers of new errata items added since the last errata addendum are

boldfaced.

Section/Page

Changes

12.5, 12-27

In the second row of Table 12-5, add a footnote at the end of the

sentence that states:

At power-on reset, port pin states are not defined in any particular

state until CLKOUT is present for two clocks.

22, 22-1

The last sentence in the last paragraph should be removed.

22.16, 22-15

In the RZS field (bit 7) of Table 22-9, for selection 1, the second

sentence in the paragraph (making reference to V.14 applications)

should be removed.

For More Information On This Product,

Go to: www.freescale.com

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