Datasheet > MPC860TVR80D4

MPC860TVR80D4

更新时间： 2024-01-18 18:37:01

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
78页	529K
描述
PowerQUICC, 32 Bit Power Architecture, 80MHz, Communications Processor, 0 to 95C

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数据手册

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MPC860TVR80D4 数据手册

Features

2 Features

The following list summarizes the key MPC860 features:

•

Embedded single-issue, 32-bit core (implementing the Power Architecture technology) with

thirty-two 32-bit general-purpose registers (GPRs)

— The core performs branch prediction with conditional prefetch without conditional execution.

— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)

– 16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instruction

caches are two-way, set-associative with 128 sets.

– 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are

two-way, set-associative with 128 sets.

– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)

cache blocks.

– Caches are physically addressed, implement a least recently used (LRU) replacement

algorithm, and are lockable on a cache block basis.

— MMUs with 32-entry TLB, fully-associative instruction, and data TLBs

— MMUs support multiple page sizes of 4-, 16-, and 512-Kbytes, and 8-Mbytes; 16 virtual

address spaces and 16 protection groups

— Advanced on-chip-emulation debug mode

Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

32 address lines

•

Operates at up to 80 MHz

Memory controller (eight banks)

— Contains complete dynamic RAM (DRAM) controller

— Each bank can be a chip select or RAS to support a DRAM bank.

— Up to 15 wait states programmable per memory bank

— Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory

devices

— DRAM controller programmable to support most size and speed memory interfaces

— Four CAS lines, four WE lines, and one OE line

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbytes to 256 Mbytes)

— Selectable write protection

— On-chip bus arbitration logic

•

General-purpose timers

— Four 16-bit timers or two 32-bit timers

— Gate mode can enable/disable counting

— Interrupt can be masked on reference match and event capture.

MPC860 PowerQUICC Family Hardware Specifications, Rev. 9

Freescale Semiconductor

1 234 5 6 7...78

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