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MPC5604BEMLLR PDF预览

MPC5604BEMLLR

更新时间: 2024-09-13 20:15:39
品牌 Logo 应用领域
恩智浦 - NXP 时钟微控制器外围集成电路
页数 文件大小 规格书
72页 971K
描述
32-BIT, FLASH, 60MHz, MICROCONTROLLER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-100

MPC5604BEMLLR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-100
针数:100Reach Compliance Code:compliant
HTS代码:8542.31.00.01风险等级:5.62
具有ADC:YES其他特性:ITS ALSO OPERATES AT 5 V
地址总线宽度:位大小:32
最大时钟频率:16 MHzDAC 通道:NO
DMA 通道:YES外部数据总线宽度:
JESD-30 代码:S-PQFP-G100长度:14 mm
I/O 线路数量:79端子数量:100
最高工作温度:125 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
电源:3.3/5 V认证状态:Not Qualified
RAM(字节):32768ROM(单词):524288
ROM可编程性:FLASH座面最大高度:1.7 mm
速度:60 MHz子类别:Microcontrollers
最大压摆率:150 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:14 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

MPC5604BEMLLR 数据手册

 浏览型号MPC5604BEMLLR的Datasheet PDF文件第2页浏览型号MPC5604BEMLLR的Datasheet PDF文件第3页浏览型号MPC5604BEMLLR的Datasheet PDF文件第4页浏览型号MPC5604BEMLLR的Datasheet PDF文件第5页浏览型号MPC5604BEMLLR的Datasheet PDF文件第6页浏览型号MPC5604BEMLLR的Datasheet PDF文件第7页 
Freescale Semiconductor  
Data Sheet: Advance Information  
Document Number: MPC5604BC  
Rev. 4, 08/2009  
MPC5604B/C  
208 MAPBGA  
(17 x 17 x 1.7 mm)  
MPC5604B/C  
Microcontroller Data Sheet  
144 LQFP  
(20 x 20 x 1.4 mm)  
100 LQFP  
(14 x 14 x 1.4 mm)  
32-bit MCU family built on the Power Architecture™ for  
automotive body electronics applications  
Up to 6 enhanced full CAN (FlexCAN) modules  
with configurable buffers  
1 inter IC communication interface (I2C) module  
Features:  
Up to 123 configurable general purpose pins  
supporting input and output operations (package  
dependent)  
Single issue, 32-bit CPU core complex (e200z0)  
— Compliant with the Power Architecture™  
embedded category  
Real Time Counter (RTC) with clock source from  
128 kHz or 16 MHz internal RC oscillator  
supporting autonomous wakeup with 1 ms  
resolution with max timeout of 2 seconds  
— Includes an instruction set enhancement  
allowing variable length encoding (VLE) for  
code size footprint reduction. With the optional  
encoding of mixed 16-bit and 32-bit  
Up to 6 periodic interrupt timers (PIT) with 32-bit  
counter resolution  
instructions, it is possible to achieve significant  
code size footprint reduction.  
1 System Module Timer (STM)  
Up to 512 Kbytes on-chip flash supported with the  
flash controller  
Nexus development interface (NDI) per IEEE-ISTO  
5001-2003 Class Two Plus standard  
Up to 48 Kbytes on-chip SRAM  
Device/board boundary Scan testing supported with  
per Joint Test Action Group (JTAG) of IEEE (IEEE  
1149.1)  
Memory protection unit (MPU) with 8 region  
descriptors and 32-byte region granularity  
Interrupt controller (INTC) with 148 interrupt  
vectors, including 16 external interrupt sources and  
18 external interrupt/wakeup sources  
On-chip voltage regulator (VREG) for regulation of  
input supply for all internal levels  
Frequency modulated phase-locked loop (FMPLL)  
Crossbar switch architecture for concurrent access to  
peripherals, flash, or RAM from multiple bus  
masters  
Boot assist module (BAM) supports internal flash  
programming via a serial link (CAN or SCI)  
Timer supports input/output channels providing a  
range of 16-bit input capture, output compare, and  
pulse width modulation functions (eMIOS-lite)  
10-bit analog-to-digital converter (ADC)  
3 serial peripheral interface (DSPI) modules  
Up to 4 serial communication interface (LINFlex)  
modules  
This document contains information on a product under development. Freescale reserves the  
right to change or discontinue this product without notice.  
© Freescale Semiconductor, Inc., 2009. All rights reserved.  

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