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MPC5604BF1CLH4R PDF预览

MPC5604BF1CLH4R

更新时间: 2024-09-13 15:45:23
品牌 Logo 应用领域
恩智浦 - NXP 时钟外围集成电路
页数 文件大小 规格书
107页 1020K
描述
32-BIT, FLASH, 48MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BCD, LQFP-64

MPC5604BF1CLH4R 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LFQFP,针数:64
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.63具有ADC:YES
地址总线宽度:位大小:32
最大时钟频率:16 MHzDAC 通道:NO
DMA 通道:YES外部数据总线宽度:
JESD-30 代码:S-PQFP-G64长度:10 mm
I/O 线路数量:45端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK认证状态:Not Qualified
ROM可编程性:FLASH座面最大高度:1.6 mm
速度:48 MHz最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:10 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

MPC5604BF1CLH4R 数据手册

 浏览型号MPC5604BF1CLH4R的Datasheet PDF文件第2页浏览型号MPC5604BF1CLH4R的Datasheet PDF文件第3页浏览型号MPC5604BF1CLH4R的Datasheet PDF文件第4页浏览型号MPC5604BF1CLH4R的Datasheet PDF文件第5页浏览型号MPC5604BF1CLH4R的Datasheet PDF文件第6页浏览型号MPC5604BF1CLH4R的Datasheet PDF文件第7页 
Freescale Semiconductor  
Data Sheet: Advance Information  
Document Number: MPC5604BC  
Rev. 12, 04/2014  
MPC5604B/C  
144 LQFP  
208 MAPBGA  
(20 x 20 x 1.4 mm)  
(17 x 17 x 1.7 mm)  
MPC5604B/C  
Microcontroller Data Sheet  
Features  
100 LQFP  
64 LQFP  
(14 x 14 x 1.4 mm)  
(10 x 10 x 1.4 mm)  
Up to 6 enhanced full CAN (FlexCAN) modules  
with configurable buffers  
Single issue, 32-bit CPU core complex (e200z0)  
®
2
— Compliant with the Power Architecture  
1 inter IC communication interface (I C) module  
embedded category  
Up to 123 configurable general purpose pins  
supporting input and output operations (package  
dependent)  
— Includes an instruction set enhancement  
allowing variable length encoding (VLE) for  
code size footprint reduction. With the optional  
encoding of mixed 16-bit and 32-bit  
Real Time Counter (RTC) with clock source from  
128 kHz or 16 MHz internal RC oscillator  
supporting autonomous wakeup with 1 ms  
resolution with max timeout of 2 seconds  
instructions, it is possible to achieve significant  
code size footprint reduction.  
Up to 512 KB on-chip code flash supported with the  
flash controller and ECC  
Up to 6 periodic interrupt timers (PIT) with 32-bit  
counter resolution  
64 (4 × 16) KB on-chip data flash memory with ECC  
Up to 48 KB on-chip SRAM with ECC  
1 System Module Timer (STM)  
Nexus development interface (NDI) per IEEE-ISTO  
5001-2003 Class Two Plus standard  
Memory protection unit (MPU) with 8 region  
descriptors and 32-byte region granularity  
Device/board boundary Scan testing supported with  
per Joint Test Action Group (JTAG) of IEEE (IEEE  
1149.1)  
Interrupt controller (INTC) with 148 interrupt  
vectors, including 16 external interrupt sources and  
18 external interrupt/wakeup sources  
On-chip voltage regulator (VREG) for regulation of  
input supply for all internal levels  
Frequency modulated phase-locked loop (FMPLL)  
Crossbar switch architecture for concurrent access to  
peripherals, flash memory, or RAM from multiple  
bus masters  
Boot assist module (BAM) supports internal flash  
programming via a serial link (CAN or SCI)  
Timer supports input/output channels providing a  
range of 16-bit input capture, output compare, and  
pulse width modulation functions (eMIOS-lite)  
10-bit analog-to-digital converter (ADC)  
3 serial peripheral interface (DSPI) modules  
Up to 4 serial communication interface (LINFlex)  
modules  
This document contains information on a product under development. Freescale reserves the  
right to change or discontinue this product without notice.  
© Freescale Semiconductor, Inc., 2009-2014. All rights reserved.  

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