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MPC5517GAVMG80 PDF预览

MPC5517GAVMG80

更新时间： 2024-11-01 21:03:39
品牌 Logo 应用领域
恩智浦 - NXP 微控制器外围集成电路
页数 文件大小 规格书
54页 616K
描述
Freescale 32-bit MCU, Power Arch, 1.5MB Flash, 80MHz, -40/+105degC, Automotive Grade, MAPBGA 208

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MPC5517GAVMG80 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：TransferredReach Compliance Code：compliant
ECCN代码：3A991.A.2HTS代码：8542.31.00.01
风险等级：5.69位大小：32
CPU系列：E200JESD-30 代码：S-PBGA-B208
JESD-609代码：e2湿度敏感等级：3
端子数量：208最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA208,16X16,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：260电源：5 V
认证状态：Not QualifiedRAM（字节）：81920
ROM（单词）：196608ROM可编程性：FLASH
速度：80 MHz子类别：Microcontrollers
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver (Sn/Ag)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：40uPs/uCs/外围集成电路类型：MICROCONTROLLER, RISC
Base Number Matches：1

MPC5517GAVMG80 数据手册

 浏览型号MPC5517GAVMG80的Datasheet PDF文件第2页浏览型号MPC5517GAVMG80的Datasheet PDF文件第3页浏览型号MPC5517GAVMG80的Datasheet PDF文件第4页浏览型号MPC5517GAVMG80的Datasheet PDF文件第5页浏览型号MPC5517GAVMG80的Datasheet PDF文件第6页浏览型号MPC5517GAVMG80的Datasheet PDF文件第7页 
Freescale Semiconductor  
Data Sheet: Technical Data  
Document Number: MPC5510  
Rev. 4, 7/2014  
MPC5510  
LQFP–144  
MAPBGA–208
20 mm x 20 mm  
17mmx17mm
LQFP–176  
24 mm x 24 mm  
MPC5510 Microcontroller  
Family Data Sheet  
MPC5510 Family Features  
• Up to 144 configurable general purpose pins supporting  
input and output operations and 3.0V through 5.5V supply  
levels  
• Real-time counter (RTC_API) with clock source from  
external 32-kHz crystal oscillator, internal 32-kHz or  
16-MHz oscillator and supporting wake-up with selectable  
1-second resolution and > 1-hour timeout, or 1-millisecond  
resolution with maximum timeout of one second  
• Up to eight periodic interrupt timers (PIT) with 32-bit  
counter resolution  
• Single issue, 32-bit CPU core complex (e200z1)  
– Compliant with the Power Architecture™ embedded  
category  
– Includes an instruction set enhancement allowing  
variable length encoding (VLE) for code size footprint  
reduction. With the optional encoding of mixed 16-bit  
and 32-bit instructions, it is possible to achieve  
significant code size footprint reduction.  
• Up to 1.5-Mbyte on-chip flash with flash control unit  
(FCU)  
• Up to 80 Kbytes on-chip SRAM  
• Nexus development interface (NDI) per IEEE-ISTO  
5001-2003 Class Two Plus standard  
• Device/board test support per Joint Test Action Group  
(JTAG) of IEEE (IEEE 1149.1)  
• On-chip voltage regulator (VREG) for regulation of 5V  
input to 1.5V and 3.3V internal supply levels  
• Optional e200z0, second Power Architecture based I/O  
processor with VLE instruction set  
• Memory protection unit (MPU) with up to sixteen region  
descriptors and 32-byte region granularity  
• Interrupt controller (INTC) capable of handling  
selectable-priority interrupt sources  
• Frequency modulated Phase-locked loop (FMPLL)  
• Crossbar switch architecture for concurrent access to  
peripherals, flash, or RAM from multiple bus masters  
• 16-channel enhanced direct memory access controller  
(eDMA)  
• Optional FlexRAY controller  
• Optional external bus interface (EBI) module  
• Boot assist module (BAM) supports internal flash  
programming via a serial link (CAN or SCI)  
• Timer supports input/output channels providing a range of  
16-bit input capture, output compare, and pulse width  
modulation functions (eMIOS200)  
• Up to 40-channel 12-bit analog-to-digital converter (ADC)  
• Up to four serial peripheral interface (DSPI) modules  
• Media Local Bus (MLB) emulation logic (works with two  
DSPIs, the e200z0, the eDMA, and system RAM to create  
a 3-pin or 5-pin 256Fs MLB protocol)  
• Up to eight serial communication interface (eSCI) modules  
• Up to six enhanced full CAN (FlexCAN) modules with  
configurable buffers  
2
• One inter IC communication interface (I C) module  
This document contains information on a product under development. Freescale reserves the  
right to change or discontinue this product without notice.  
© Freescale Semiconductor, Inc., 2007-2014. All rights reserved.  
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