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MM74HC73 PDF预览

MM74HC73

更新时间: 2024-11-16 05:08:31
品牌 Logo 应用领域
美国国家半导体 - NSC 振荡器
页数 文件大小 规格书
6页 129K
描述
Dual J-K Flip-Flops with Clear

MM74HC73 数据手册

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January 1988  
MM54HC73/MM74HC73  
Dual J-K Flip-Flops with Clear  
General Description  
These J-K Flip-Flops utilize advanced silicon-gate CMOS  
technology. They possess the high noise immunity and low  
power dissipation of standard CMOS integrated circuits.  
These devices can drive 10 LS-TTL loads.  
All inputs are protected from damage due to static dis-  
and ground.  
charge by internal diode clamps to V  
CC  
Features  
Y
These flip-flops are edge sensitive to the clock input and  
change state on the negative going transition of the clock  
pulse. Each one has independent, J, K, CLOCK, and  
CLEAR inputs and Q and Q outputs. CLEAR is independent  
of the clock and accomplished by a low level on the input.  
Typical propagation delay: 16 ns  
Y
Wide operating voltage range: 26V  
Y
Y
Y
Low input current: 1 mA maximum  
Low quiescent current: 40 mA (74HC Series)  
High output drive: 10 LS-TTL loads  
The 54HC/74HC logic family is functionally as well as pin-  
out compatible with the standard 54LS/74LS logic family.  
Connection and Logic Diagrams  
Truth Table  
Dual-In-Line Package  
Inputs  
Outputs  
CLR  
CLK  
J
K
Q
Q
L
X
X
L
X
L
L
Q0  
H
H
Q0  
L
H
H
H
H
H
v
v
v
v
H
H
L
L
H
H
X
L
H
H
X
TOGGLE  
Q0 Q0  
Top View  
TL/F/5072–1  
Order Number MM54HC73 or MM74HC73  
TL/F/5072–2  
TL/F/5072–3  
(1 of 2)  
C
1995 National Semiconductor Corporation  
TL/F/5072  
RRD-B30M115/Printed in U. S. A.  

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